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Questions related from Mukesh Kumar
I am interested in the structure of the ELT NMOS transistor.
16 May 2021 8,398 2 View
For the read operation, the WL will be at logic high (Vdd or let 1V) and initial condition at internal nodes (let Q and QB) are 0 and 1 V. The BL and BLB are also precharged to logic high....
15 July 2020 9,661 8 View
Please, suggests me the possible answer with an explanation or any supplementary document.
14 April 2020 7,801 0 View
Describe the physical significance of Post layout simulation in Cadence virtuoso .
25 December 2018 3,515 4 View
I am in need to finalize the operating frequency of SRAM cell, when working with Cadence vituoso software and pulse wise linear (pwl) supply is used. please give me valuable suggestion how to...
30 October 2018 7,705 5 View