Dear Ebadur,

you can try to secure the performance and functionality of your pll with transient simulation. Start with Ultrasim until you approach the locking of your pll and take over (save the operating point bevor) with spectre for accuracy. Combine all available cases with voltage and temperature variations within the frequency range.

(Sorry, is a lot of work)

Some theory can be found:

https://aicdesign.org/wp-content/uploads/2018/08/01_pll_180809.pdf

Best Regards

Bernd

Hello Ebadur,

Let me start with a question: Why do you think that "we can not perform just AC analysis or STB analysis of Cadence to find the stability of the PLL loops." ?

When the PLL has locked, we can apply the classical linear PLL model. Therefore, we also can apply the classical stability criteria (Nyquist, Bode) to analyze the stability properties of the closed-loop system.

As far as your last question is concerned, I think it is interesting to verify the pull-in properties of the PLL system when it is NOT in locked condition.

In the attached example (pdf file) the nominal PLL frequency is fn=50kHz. It can be seen that the PLL is tuned to an externally applied reference frequency of 56 kHt within a pull-in time of 3ms.

Hi Lutz,

When the PLL is locked the clock is still going up and down for both references and feedback right?

When we do the ac analysis or stb analysis we give basically a dc operating bias point then, over it we impose an ac signal, then we calculate the gain and phase.

How may we perform that on PLL? To be it in phase locked or in operation in transient time both the clocks should toggle upto VDD to VSS,

and in AC analysis like we did on op amp, we do not give swing upto that.

I maybe in lack of basic, thats why my question may sound stupid, hope you can clarify.

Hi Ebadur,

What I have forgotten to mention is the following:

* The linear PLL model (to be applied under locked conditions only) is valid for PHASE information (input and output) only. That means: The transfer function is the ratio of two phase informations (and not voltages).

* This will complicate the simualtions for real circuits. I did all simulations for block diagram representations only - hence, with no biasing problems.

Hi Lutz,

Ya I was talking about the real circuit, implemented in CMOS but good to know it is applied for the phase.

First of all Cadence is a company, so if you want use cadence to simulate your PLL sign proper contract with them.

Depending to simulator software, stability of PLL can be directly checked by PSTB or PAC analysis, if available.

If you are using Spectre and have a licence for SpectreRF than you can use it. Information how to use these analysis are placed in manual, of course. SpectreRF installation directory contains also examples and tutorials.

Hi Dominik Przyborowski

Thanks for your reply, it is available.