Power consumption typically has 2 terms: static consumption (@ frequency 0 Hz) and dynamic consumption (e.g. expressed in (µ,m,)amps/MHz). Static consumption scales linearily with the operating voltage, dynamic consumption today (with MOS semiconductions) scales roughly with the square of the operating volage (as most dynamic losses stem from charging/discharging capacitances).

For a given circuit the power consumption can only be influenced by changing the operating voltage. In guess your "... but the oscillation frequency will decrease ..." is a bit of a misunderstanding: The maximum OPERATING frequency depends on the operating voltage: due to resistances and other parasitics there is always a voltage where the charging/discharging of capacitances within a given period of time is no longer possible. This point defines the minimum operation voltage. Operating a circuit with a voltage beyond this minimum is possible (if not overheating), but generally a waste of energy.

The other means ? change the circuit elements, design a new IC (with typically smaller geometries) and so on.

As stated on top: for a GIVEN circuit the operating voltage is the only parameter.

Dear Dreher,

Can you explain me in details ?

The maximum OPERATING frequency depends on the operating voltage: due to resistances and other parasitics there is always a voltage where the charging/discharging of capacitances within a given period of time is no longer possible?

Hello,

may I kindly redirect you to the answers of your other question ?

https://www.researchgate.net/post/CMOS_high_frequency_and_low_frequency_circuits

Prof. Zekry's answer there should be clear.

Trying a different approach: digital signal propagation depends on switching the output voltage level of one element over/under the input threshold of the next element. To achieve this, parasitic capacitances have to be charged resp. discharged. The energy in a capacitor is 1/2*C*U².

Important as well is that every switch has some output resistance that also depends on the operating voltage (typically: higher voltage -> lower resistance). Thus the RC time constant depends on the operating voltage: higher voltage, lower RC - thus faster operation.

Hope you got the concept

Pdynamic = CVDD2 f. By reducing parasitic and load capacitances one can reduce power consumption at high frequencies in addition to low VDD and low frequency.

Pstatic = VDD*Ileak. To reduce static power consumption, reduce VDD and the number of transistors involved.

1. One more way to reduce power consumption even at high frequency and higher supply voltage is to cutoff portions of a circuit or system during idle mode by either employing clock gating (stop the clock reaching a given module) or power gating (blocking power supply to reach a given block).

2. The overall power consumption is also minimized  in  chips today by going for dynamic supply voltage (DVS scaling) and dynamic frequency scaling (DFS) where both the supply voltage and frequency are adjusted for different blocks of the chip depending upon their realtime throughput requirements.