In this FSK the frequency is shifted from 90khz to 100khz. the Baud rate is 4800 or lesser. Noise immunity is important for the final design. Is there any measure of this?
I never did it before and do not really know how it is "normally" implemented.
Thinking about the problem I'd try it the following way:
This is not exactly the PLL way, but doable with quite a number of microcontrollers with little hardware presumptions. But it will create quite some processor load.
thanks Dreher. I need to also address how to generate the 90 and 100 kHz using the uC
Dear Mani,
You can build your PLL as all digital PLL, where the the voltage controlled oscillator is made to generate two frequencies say fm and fs with fm=100 kHz and fs= 90KHz, The two frequencies can be digitally synthesized by storing the sine wave samples and reading them with the appropriate speed and starting them with the correct phase according to the phase detector output. The loop filter and the phase frequency detector are built from digital building blocks from digital circuits.
The all digital phase locked loop can be constructed in software that can be executed by the micro controller.
For more information please follow the Link:http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L080-ADPLL(2UP).pdf
and the link:http://epubl.ltu.se/1402-1617/2006/284/LTU-EX-06284-SE.pdf
Best wihes
Dear Zekry, Thanks for the link and the thesis. I Shall go through and should be able to find the answer I am seeking. Thanks again
Dear Dreher, Thanks for the response.
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