Hi

Look at link

http://electronics.stackexchange.com/questions/29902/w-l-ratio-of-a-mosfet

Generally , the minimum W/L ratio of pmos to nmos is 2.5 times.

But in order to have smooth performance , the W/L ratio of pmos is usually kept higher than 2.5.

It depends different parameters.

1.       The gate length specified for a MOSFET technology means the MINIMUM length. In design it can be larger than the minimum length.

2.       The W/L ratio is linked to the trans-conductance and the current capability, together with the multiplicity factor m. A higher w/l ratio increases the current gain and subsequently a higher current for a given Vg.  The same is for a higher m that means m·W/L.

3.       In practice, for the gain stages are useful large transistors, i.e. large W/L ratios or/and large m. As example, the differential input stage of OpAmps needs high gain. However, the good matching of the input differential stage has to be considered as well.  

4.       In the current mirrors, a higher transistor gate length is beneficial, for a better matching of the mirror’s currents. You can play with these parameters in simulations to observe the impact of the length on the mirrors current matching.

5.       In general, a larger transistor ensures a better matching because it minimizes the edge effects, but this is paid with a significant area price.

Thank you very much!

Generally gm/Id techniques is used to find the W/L ratio of MOS transistors.

You need to understand the geometrical sensitivity of your circuit. So if it is a biasing circuit, i.e. current mirror, or a current source that needs to match to another source on the die, then you need to increase the length and make the width a nominal say 5um and then use multiple legs to accomplish the sizing. Make sure all transistors that are to match have the same orientation and layout and only differ in the multiplier. Minimum length and width devices have poor matching!

By using the design parameters from dc operating analysis and gate to source voltage in the current (Id) equation, w/l can be found.

with the caveat not to ever use minimum L and more importantly follow my advice to lay out unit size devices and use multiple if them for scaling and add dummies on the outside so the scattering effects from the Plasma Etcher scattered at the mask boundaries do not cause Well Proximity Effects or WPE causing the outer devices to run hotter than the inner devices. Been there done that. SO be careful.

Most modern processes have these WPE problems and the device generators are all oriented to digital design so they will kill your matching.

Check this paper for step-by-step procedure to design an OTA (selecting L and W of each transistor).

https://www.sciencedirect.com/science/article/pii/S0026269217307905

You can also use gm/id design methodology. that's very useful to design high-performance OTAs.

Here is an article about gm/id method:

Article Optimizing Operational Amplifiers by Evolutionary Algorithms...

In constant current applications, like the current sources, adjust the w/l ratio based on the desired overdrive voltage and allowable swing. In other applications, in which bandwidth is required to be enhanced, w/l is enlarged proportional to the increased current to yield resonable voltage swing.

Check these papers for the step-by-step procedure to design an OTA, Op-Amp and CCII (selecting L and W of each transistor).

Article Design of CNTFET based CCII using gm/ID technique for low vo...

Article Systematic design of CNTFET based OTA and Op amp using gm/ID technique

According to the operating point for the transistor i.e. vgs, vds, and Ids you can choose the W/L ratio considering the small signal parameters like gm as well.

By default, the gate length is given by its (process) minimum length. Minimum length is beneficial for minimum capacitance but causes higher phase noise. In design, it can be increased based on the applications. Normally, for high-frequency applications, we use minimum length since we need minimum capacitance for a higher frequency of operation. On the other hand, for current mirror applications, a larger W/L ratio is preferable for better matching of reference current and mirror's current (minimizes the edge effects), though it will cost a significant chip area.

The W/L ratio is related to transconductance (gm) which is defined as the ratio of the change in drain current to the change in gate-source voltage. So for a given gate-source voltage, a higher W/L ratio results in a higher current. If we see the equation for MOSFET drain current in saturation

Id=1/2uCoxW/L (Vgs-Vth)2

From here easily understandable that W/L increases the current for a given gate-source voltage.

We know the equation for transconductance (though have another two forms)

gm=root(2*uCox*W/L*ID)

assume, uCox = 200uA/V2; ID=1mA

then for gm=2.5mA/V,

W/L= gm2/(2*uCox*ID)=15.625

In summary, I can say transconductance and W/L are proportional to each other and for a given bias current and process parameter, W/L can be calculated if transconductance value is known or vice versa.

The W/L ration of the MOSFET can be determined with the value of trans-conductance

That depends upon technology parameters, required trans-conductance gain and also the amount of current needed in that branch

Rangeetha Jabez If I have gm=2.5mA/V how can I determine W/L ratio from it?

Can you kindly explain your point?

Adeel Ali, I think Rangeetha Jabez and Tajinder Singh Arora are right. I just add the equation and the calculation with their comments with due respect.

We know the equation for transconductance (though have another two forms)

gm=root(2*uCox*W/L*ID)

assume, uCox = 200uA/V2; ID=1mA

then for gm=2.5mA/V,

W/L= gm2/(2*uCox*ID)=15.625

In summary, I can say transconductance and W/L are proportional to each other and for a given bias current and process parameter, W/L can be calculated if transconductance value is known or vice versa.