I used to do my programs in behavioral description type as functions. Fortunately, I could call functions inside another function. Then I realized that they are not synthesizable. After that I tried port mapping and I had so many components with each having distinct names in my program. The problem is that when I write my statements inside my program, I could not call other components using port mapping (illegal!).
Hi,
My first suggestion is that you have to stop thinking about hardware modelling with VHDL as a programming. This is the primary source of your problems.
A VHDL model with multilevel hierarchy is something absolutely legal and it should work with any CAD tool, both in simulation and synthesis. But the hierarchy have to be implemented using "entity" instead of "funtion" statement.
I suggest you look at tutorials on logic modeling with VHDL and pay attention to section called "Structural Description", e.g.
http://www.altera.com/support/examples/vhdl/vhdl.html
http://www.altera.com/literature/manual/stx_cookbook.pdf
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html
http://users.ece.gatech.edu/sudha/book/starters-guide/
Regards,
Zbigniew Jaworski
It is legal in VHDL. I guess you made some minor mistake while doing the VHDL programs