This file is usually generated by Qsys (or SOPC Builder in older Quartus versions). If the project you are talking about is this one - http://www1.cs.columbia.edu/~sedwards/classes/2012/4840/lab2.tar.gz - then you will need the get an old version of Quartus, because it was made using SOPC Builder, which is no longer supported as far as I know. Perhaps the last version of Quartus supporting SOPC was v12.1. Once you get a Quartus version which comes with SOPC Builder, you can launch it from the Tools menu, open the nios_0.sopc file and generate the system.

 Hello Paulo,

I am grateful for the useful directives offered. I am currently making some progress with Quartus 9.1 and will report on the final outcome. 

initially, I loaded  the nios_0.sopc without the supporting folders and files. SOPC Builder complained about the components eg PS/2 etc being not found. But, I later included all the files and folders with SUCCESS but with about 10 warnings.

I am currently generating  nios_0.qip

 Hello Paulo,

I am grateful for the useful directives offered. I am currently making some progress with Quartus 9.1 and will report on the final outcome. 

initially, I loaded  the nios_0.sopc without the supporting folders and files. SOPC Builder complained about the components eg PS/2 etc being not found. But, I later included all the files and folders with SUCCESS but with about 10 warnings.

I am currently generating  nios_0.qip

Hello Paulo,

I succeeded with the generation of nis_0.qip.  GREAT!

Hello Paulo,

These are the new set of errors from compiling the nios_0.v.

Error: Node instance "the_DM9000A" instantiates undefined entity "DM9000A"

Error: Node instance "the_I2C_0" instantiates undefined entity "I2C_0"

Error: Node instance "wrapper" instantiates undefined entity "ISP1362_IF"

Error: Node instance "the_SEG7_Display" instantiates undefined entity "SEG7_Display"

Error: Node instance "the_sram_0" instantiates undefined entity "sram_0"

Kindly help out.

Ayodeji

Hi Ayodeji,

That's strange, the DM9000A.v, I2C_0.v, ISP1362_IF.v, SEG7_Display.v and sram_0.v files which are missing should also have been automatically generated. Please try to copy these files from the DE2_NET demonstration which can be found here:

http://users.ece.gatech.edu/~hamblen/DE2/DE2_demonstrations/DE2_NET/

(it's originally a demonstration from the DE2-70 demonstrations CD)

As you can see from the file contents, these are all very simple structural Verilog modules (that serve as wrappers) which should have been automatically generated by Quartus/SOPC Builder.

Best regards