Fixed and floating point date type synthesizable HDL code what are the diff ways/tricks/new& diff ideas that a fixed or floating point algorithm can be implemented in FPGA using Verilog and the same for VHDL
For the betterment of student and professionals:SInce this info is not fully/widely available in book only engineers who were working in FPGA embedded system application development knows better ways and possibilities with current technical advancements.
i give some ans, others can suggest their innovative ways and easy ways
1. Verilog real data type is only for simulation hence convert all into a BIGGG sized integer which hold the full value number with enough value precision ,as integer data type is synthesizble. (actually look for the lowest value , find how much 10's should be multiplied to make it integer , multiply this number to all the variables and constant in the algo)
2.VHDl offers fixed and float point package which is synthesizable , we use that for algo in VHDL , i think this is extendable for verilog also
3.if u know C u can write in C verify functionality in any digital tool or matlab and use xilinx HLS to make a HDL conversion that is synthesizable.
4.algo can be written straight forwardy as a set of equations in MATLAB , after verification use ,HDL tool ,Fixed point tool , simulink HDL coder to generate , HDLsome more ways ,
will discuss later , hope to receive new ways/ideas and possibilities from other company tools to do the above
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