There are many research papers on process variations and aging affects on CMOS and FinFETs. However, I would like to have an opinion on this forum about what are the significant process parameters which can affect the circuit reliability? In my opinion: Fill in the blanks with your valuable comments:
For CMOS Process Parameters: TOXE, Leff, Weff and ___,___,___?
For FinFETs Process Parameters: TOXE, Lg, HFIN, TFIN, PHIG and ___,____,_____?
If the above are wrong in your opinion please comment on them as well.
Thank you.
For CMOS devices, effects such as Random Dopant Fluctuation (RDF) which impact on threshold voltage are of interest. Due to the uncorrelated nature of such effects devices may age different.
For CMOS devices there is other random mechanism called Random Charge Fluctuation that is related to the formation of a random number of trapped charges. These fluctuations increase as a function of stress time.
RDF is also significant in finFET as I found.Other than the above you mentioned, the gate shape of finFET is very dominant factor.Tpoly ,spacing between fin are also significant.
Im not sure about the effect of RDF in FinFets...
VDD scaling for conventional CMOS is limited by VTH variations (due to RDF), Nevertheless, high doping is not required for multi-gate devices such as FinFETs due to their improved Short channel Effects behavior. Thus, in FinFET devices, RDF is reduced and as consequence VTH variation is smaller and VDD can be scaled to lower voltages.
Thanks. You are right. RDF is much reduced in FinFETs but for accurate characterization we can not completely ignore it.I'll go through this more deeply.
Thanks for answers.
In literature, there are many sources of variability in FinFETs such as
Random Discrete Dopants (RDD)
Metal Gate Granularity (MGG)
Line Edge Roughness (LER)
Gate edge roughness (GER)
Fin edge roughness (FER)
However, it would be interesting to know which one of them is more error-prone to Threshold Voltage in specific.
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