First case: Since the capacitor cannot be discharged (no path parallel to the capacitor), its potential will first reach about V = VImax - VGSTH, with the maximum potential VImax of the clock signal, and the threshold voltage VGSTH between gate and source at which the MOSFET starts to conduct. Since the channel of the MOSFET cannot be switched off completely, the potential of the capacitor will slowly rise to Vdd later on. If (Vdd - VClockmin) > VGSmax, the MOSFET will be destroyed.

Second case: If the capacitor will be discharged at clock off phase, the output signal depends on the impedance of the capacitor (at clock frequency), and the characteristic of the MOSFET:

If the impedance is so high that the MOSFET doesn't enter the "current limiting" state (and if discharging is fast enough), the output signal is roughly rectangular, its AC component is in phase with the input, and its amplitude is less than that of the clock signal.

If the impedance is so low that the charging current is limited by the MOSFET, the potential of the capacitor will ramp up during the on phase. If discharging is accomplished by a resistor, the potential will follow an exp-function. It will lock like something between triangular and saw-tooth with spaces between the teeth, depending on the value of the resistor.

Of course, there is a smooth transition between high and low impedance.

Independent of impedance, the DC component of the output signal will be about 1V .. 3V lower than that of the clock signal.

Dear Biswajit,

Your circuit configuration resembles that of the pass transistor logic with the clock controls the pass transistor whose drain is connected to VDD and its source is connected to a load capacitor. The circuit resmbles also the dynamic RAM cell in case of write one operation with the capacitor in this time is the bit storage element. As Joerg n described when the clock gets high with a voltage = VDD it will be on conducting current and charge the load capacitor to a a maximum voltage = VDD- Vth with Vth threshold gate to source voltage that is required to make the transistor start conduction. The output voltage will remain almost constant with time since any loss of charges will be refreshed by the next positive clock pulses.

As for the operation when one discharge the load capacitor in the off period of the clock, since one discharges the load capacitor in the off period of the clock , it will be charged during the pulses of the clock as described in the previous state. The output voltage on the capacitor in this case will resemle that of the clock except the rise and fall times may be larger and the maximum output voltage level will be lower than VDD by the threshold voltage.

Best wishes

Dear Biswajit Singh,

The maximum voltage will be Vin-Vth and depending on input frequency and capacitance, the capacitor tries to reach the maximum voltage...

Input voltage defines the maximum charging voltage...