In the ISE design suit (14.7) there was no problems implementing the Black box to a JTAG model, but now it is important to use the Vivado, due to its many tools and facilities.
Unfortunately since the version 2015 till now everytheing works just fine in the Vivado, SDx, SDK, HLS tools, EXCEPT this Black box block in the system generator which is very useful for a DSP engineer.
the the error is shown in the picture below and it is the same in all versions:
ERROR: [IP_Flow 19-748] Component Definition 'User_Company:SysGen:bbb:1.0 (bbb)': No ports found. There must be an interface when the IP has at least one source file group. ERROR: [Ipptcl 7-1485] check_integrity: Integrity check failed. ERROR: An error occurred when creating the Vivado project. ERROR: [Common 17-39] 'ipx::check_integrity' failed...
Dear Karim Meddah
Yes there is a very simple way to add a board to the Vivado System generator, available from version 2016.1 till now.
Now I amusing Vivado 2018.2 and I added Arty A7 35T, I tested the generation of the JTAG model and the pin assignment... works just fine except for that problem I posted in this Q.
The instructions I followed for adding new board are in Page 15 of the "ug897-vivado-sysgen-user" guide.
Regards.
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