7 Questions 19 Answers 0 Followers
Questions related from Hussein M. H. Al-Rikabi
Recently a new tool was released by Xilinx wich is xilinx vitis core development kit 2019.2. is there any similar tool in Altera?
02 June 2020 3,637 0 View
hello, I have built a logic circuit and i didn't use a clock inside my block, *Now I am trying to simulate that cct to calculate the speed or latency, the ISim or Vivado simulator in the...
19 November 2019 5,456 1 View
In the ISE design suit (14.7) there was no problems implementing the Black box to a JTAG model, but now it is important to use the Vivado, due to its many tools and facilities. Unfortunately...
19 March 2019 8,016 1 View
What Device is best suited for DSP applications containing signal and Image processing? SoC or HLS might me included... I made a survey and I found Ultra96 is incomparable with any other FPGA...
26 December 2018 5,024 14 View
What would you buy for an integrated design that has loops and Logic that need to be implemented with a very high rate? What are the Pros and Cons of both?
14 December 2018 6,896 4 View
What FPGA company do you prefer? What are you using any of them for? What suggestions you can offer to improve any of them?
04 December 2018 2,868 20 View
Hello friends, Has anyone tried the new Xilinx Vitis Core Development Kit? Does the TensorFlow work fine with it? If you have any links of videos.. please share with a comment.
01 January 1970 8,476 0 View
