I simulated a CMOS design using 45 nm technology. With increase in supply voltage there is a gradual increment in delay has been observed? why the delay is increased with increment of supply voltage? what is the relationship between delay and supply voltage and why it happens?
Very much simplified, but illustrating the principle: Higher voltage means you require more energy to charge and discharge every capacitance, energy is proportional to V2, but current only increases with V.
Thanks for your answer sir. But in my design the delay also increasing while increasing voltage. I do not know the reason. what may be the reason?
Which delay do you mean?
The gate switching takes longer time, since more charge has to be moved.
Line delay is also increased, since every wire has a capacitance.
Also, you have a larger field in the conducting transistor, so you have more charge carriers in the channel to get rid of when closing the gate.
Hope this helps
Olof
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