I have been using silicon alloy anode material. When I made impedance measurement using half cell at three different bias voltage 0.2,0.4,0.9V, I found that I had an inductive artifact in the low frequency region of the nuquist plot. Initially I thought it was due to cell geometry so I switched from El cell to tcell type, then the low frequency loop disappeared but interestingly now I get high frequency inductive loop at the begining. This loop gradually disappeared with cycling. the loop at 0.2V disappers after 5 cycles but the loops at 0.4V and 0.9V disappears after 10 and 15 cycles respectively. Is it because of SEI layer stabilization? Then why do I need loop at high frequency rather than low frequency region.
Your high-frequency inductive reactance is caused by the loops in the wiring (Faraday's law of induction). Basically, any circuit forms a loop with a non-zero area. (If anything, the dielectric jacket, shielding and outer jacket cause the are between the inner conductors of any two coaxial cables to be non-zero.) You need to minimize the area of any loop created by wires and connectors. (For example, for a 4-wire connection geometry as you would have on a Solartron or HP/Agilent instrument, use the thinnest possible 50 ohm coaxial cables, e.g., RG196 with 2 mm OD, and twist them closely together.) There also exists a Hewlett-Packard application booklet which explains how to perform an open-short-load correction for your impedance measurement setup. The equations are given in the attached Microsoft Word document.
Thank you for the concise explanation Dr. Halalay. It was so informative. Apart from cell geometry, is there any other reason for this inductive behavior?. Becuase the inductive loop disappears with aging. The size of the loop differs from the delithiated state to lithiated state.
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