I read many books and search on Internet but I did not find any answer .
I don't have the specifics on 8085, but in general machines have a multi-stage pipeline of instruction decoding, and older machines do not have adaptive jump predictors.
In a jump, either the TRUE or FALSE outcome can be optimized, because one of them is going to cause the pipeline to be flushed. Since the most common decision in normal code is for loop control, and the most common outcome of a loop comparison is to take the jump (not fall out of the loop), it is a good performance bet to optimize taking the jump (back to the top of the loop).
Now even if that is not the exact explanation for the 8085, a performance bias between jumping and falling is something you can learn to take advantage of in your code, if you have a code path you want executed as fast as possible then any decision to jump can be inverted and made a decision to not jump.
I say "a path" because it does not necessarily have to be the most probable path or the one that would minimize average execution time; in some optimization cases for real time operation, you may want to minimize the longest paths so they fit within your execution window, even at the expense of increasing the average path, as long as it remains in the execution window.
In false condition it will not fetch address to jump so it will take less T states.
While in true condition it need additional information about where to jump sonit take 3 extra T states
Dear Nitin Mathur,
I hope you have your answer by now from previous answers.
I still am trying to explain the reason for conditional branching instruction 7T states if condition is not met. Why isn’t it 10 instead?
The explanation:
First of all we need to keep two things in mind
1. Each instruction has opcode fetch cycle where in first two clock pulses the memory is fetched for the opcode and it is placed on the data bus and in next clock pulses it is loaded into instruction register and subsequently to instruction decoder for interpreting the instruction.
2. The program counter always points to the next memory location from where an 8 bit data will be fetched. Processor always fetch the program counter value either as opcode fetch or normal memory read as per the previous fetching and the program counter value will automatically be incremented by 1.
Now in connection with the answer of the question:
When the opcode for a conditional jump is being fetched the PC value is pointing to the higher byte of jump address. After the 4th CP the processer automatically starts fetching the memory location pointed by the PC (Lower byte ) as a simple memory read and PC is auto incremented by 1 but as soon as the instruction decoder completes the interpretation of the conditional jump and finds the condition to be false then processor finds it unnecessary to fetch the Higher byte of address which is currently pointed by the program counter and the PC value is incremented by 1 again to point next instruction (i.e. an opcode instead of Higher byte). So at false condition there are two machine cycles, i.e. OFC + Mem read (unnecessary but have to wait to finish the cycle)
Hence it is 4+3=7
I will be glad if this info helps.
Thanks
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