There are two version of NAND and NOR cmos gate in dynamic gate design. One is N-logic based and the second one is P-logic based. Which one have to use for low power design requirement?
In addition to being faster, as conductivity is proportional to mobility an n-channel device will have half the impedance and gate capacitance of an equivalent p-channel device for the same die area. Therefore, n-channel logic can be smaller for the same complexity.
For low power design requirement you should go for N-logic based because mobility of electrons is higher and also its normally off .I think if you go P-logic there will be more leakage currents hence low power design can not be achieved.
N- logic blocks are normally used to implement dynamic CMOS logic. Only in case of single phase clock one has to use alternately P-logic blocks and N-logic blocks alternately.
The NMos logic is superior than the PMOS logic as the NMOS transistor is better than the PMOS transistor. The major advantage comes from the electron mobility is much greater than the hole mobility. un= 2.5 up. Therefore the nNOS transistors are much faster than the PMOS transistor which is very required for performing the logic operation. In addition there are two types of NMOS transistors: the enhancement and depletion where for the PMOS transistor there is only the enhancement type.
In fact the MOS transistor logic has evolved from the PMOS, then the NMOS, and finally the CMOS. With the introduction of the CMOS, one could reduce the static power consumption especially on the pull down state. That is both the pull up and pull down transistors are acting as switches.
For more precise compaeison between the different types of CMOS logic gates please refer the ppt in the link: vlsi-eda.cm.nctu.edu.tw/course/.../Lec%2012%20Dynamic%20Logic%20Circuits.ppt