The processor pause for one bus cycle

A DMA will break up its job into many short bus requests and issue sequential bus "transactions" that are a burst-length long (usually long enough to efficiently utilize DDR, but not so long as to hold off other parts of the system too long, such as the CPU) until its full task is completed.  Each of these transactions are arbitrated for control of the bus with other requesters.  So, a CPU will also be requesting access to the bus for its transactions (usually the size of a cache line) and they simply take turns at a transaction level.  Each requestor "owns" the bus only during its transaction, but then has to wait for the arbitration scheme to give it access again.  This gives the perception that many things are flowing concurrently through the system even though they are actually tightly interleaved.

A well-designed system will have enough capacity in the bus and low-latency access to memory that each requestor gets enough throughput to meet its individual needs, even when the system is relatively "busy".