Does Timing Violation in cadence RTL compiler affect the dynamic power report or what is the relation between dynamic power and timing violation?
As dynamic power is proportional to switching activity, frequency of operation, violation of these factors may cause timing violations.
Not sure what you exactly mean with the 'timing violation' as I believe there should be more than one reasons for that. Yet the report generated should not be affected by 'until' timing violation. As far as I can tell from the description, the generated data probably yields wrong values. If you can identify the source of the violation, which is most probably irrelevant to the dynamic power measurement, then you'd solve your problem.
You may want to read papers related to Power-Delay product. Faster circuits may have more gates and may hence dissipate more power. Higher clock speed can also mean higher dynamic power.
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