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Questions related from Nireesha Rasiraju
I have designed Wallace sign multiplier using reversible logic gates as well as using Irreversible gates(HA,FA,AND Gates ).I am getting power dissipation less in irreversible multiplier than...
13 September 2014 2,906 5 View
I am designing reversible logic gates and multiplier circuit using those gates. I have to calculate quantum cost for multiplier. Can anyone suggest some solution?
11 August 2014 6,527 32 View
MTCMOS technique reduces leakage power efficiently, but transistor sizing and retaining data in sequential circuit are its major drawbacks. I got to know from papers that SVL circuits reduce...
05 February 2014 7,177 0 View