We need to do additional process on a silicon wafer after having standard CMOS fabrication done. This additional process may involve high temperature (around 500 C) and take hours. Will this degrade silicon chip?
I do not know exactly the kind of circuit you have. However, it seems to me that the efficiency of your devices can be affected by doing this "extra" process. I was just looking at the following documentation:
http://www-eng.lbl.gov/~shuman/NEXT/MATERIALS&COMPONENTS/Xe_damage/Diffusionin%20siliconpdf.pdf
and it is possible to see (in Fig. 1.27) the solubility of Phosphorus already at 400°C. Therefore, I would imagine that a optimization is required for the previous process steps instead of simply add this further step.
IMEC official sad once what chips without polyimide passivation are tolerant up to 400 C. With polyimide, top temperature is 250C
500C for a few hours seems like it will affect the dopant mobility, like F.L. pointed out above. It is possible that the metallic contacts might also reflow, depending on the eutectic temperatures with Silicon of the metals used in your circuit. This can affect the contact resistances to say the least, and may degrade the saturation currents of your FETs.
I would be skeptical of the circuit performance. Can you find an alternative for your process? Otherwise, as F.L. said, you're going to have to optimize the fabrication process for this additional post-fab step.
Post processing of the CMOS chip after finishing its processing may affect its operation. The main cause is that aluminum materialization may build micro alloying with the underlying silicon and aluminum spikes may penetrate the very shallow source and drain regions. If there is silicide layer under the aluminum materialization, the CMOS chip could withstand the 500 degree annealing for a limited time. Why not making some experiment on the intended chips and observe the effects on test structures.
Best wishes
Texas Instruments makes some "enhanced" CMOS devices for which they provide de-rating charts for "Life" calculations at different temperatures. The charts include 220 Centigrade and predicts 1000 hours life at that temperature. Analog Devices may do this as well. Honeywell has been selling Silicon On Insulator (SOI) devices that will run for years at 225C junction temperatures. These can endure excursions to 300C. RelChip offers several devices in high temp SOI with similar temperature capabilities. Research is ongoing in Silicon Carbide (SiC). This technology might yield 500C components. NASA is in that research space. Theoretically, diamond (carbon) can be used to make transistors that could work at 900C.
S. Sedky, A. Witvrouw, H. Bender and K. Baert, "Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers," in IEEE Transactions on Electron Devices, vol. 48, no. 2, pp. 377-385, Feb. 2001, doi: 10.1109/16.902741.
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