Have you compared the power dissipation(Static and dynamic) of SRAM cell on different technology nodes with similar supply voltage, material (preferably CMOS) and aspect ratio. In case it increases or decreases, can you explain it with some reference or may be some mathematical evidence?
http://soiconsortium.eu/wp-content/uploads/2017/08/FDSOI-Technology-Overview_BY-Nguyen_Nanjing-Sept-22-2017_Final.pdf
Thank you so much Prof. Naushad Alam sir, for kind help. This was immensely helpful to explain one of the very important query of reviewer.
To add a few points.
The data is reflective of planar cmos where we were limited by leakage. The trends are different for 16-5nm nodes.
With finfets the leakage component has reduced significantly as compared to dynamic mostly because higher gate currents that can be drawn reducing freq limits as well as leakage contribution to total power.
So we need to break the design across 2 families with different behaviours.
Bulk with dominant leakage and 3Dgate/ finfet with dominant dynamic power.
Dear Mr. Shakir Iqbal , Thanks for support. however, i am more interested to under this in terms of CMOS only. and some plot that compares leakage of 90nm ckt down to 16nm will be a great help in this regard.
The total power dissipation of SRAM cell enhances with technology node scaling. This is because of the reduced distance between devices due to which the short channel impact comes in to the picture!
Neti Arora sir how short channel effect does this? can you please explain more?
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