I am NOT an electrical engineer, but I would say that limiting simply means that current is kept below a certain level.  The limit could be high or low.  Starving means the smallest minimum that can possible work, just like a starving person barely has enough food to survive.  

Its not my primary field. But current starving is the motivation to construct low power circuits by shrinking the size, voltage and power. Current limiting is the act to keep the current under a certain limit to prevent destructions.

Thank you for both answers.

From your replies I deduce that "starving" is - more or less - a synonym for "saving" resp. "economize"? Could this be correct?

I couldn`t find the term "starved circuit" or starved current" or "current starving" in no dictionary.

For my opinion, yes. Starving is a sparing process by construction.

I agree with Mr. Marek's analogy for 'starvation': "just enough food to survive", where 'food' can be either current or voltage being fed to the device. The term was coined during the hey days of valves (vacuum tubes). Internet reveals a recent article on 'amplifiers under starved conditions' by Mr. Merlin Blencowe with references as early as 1951.

'Limiting' has little to do with the subject above. It is usually linked (but not restricted) to some protection feature, and can be set at very high (nearly dangerous) levels which is much the opposite of the 'starving' concept. I hope this clarifies.

As stated by earlier responders, I too feel that Current Starving means just barest minimum current possible.

I agree with Prof. Flavio Bettti's agreement with Mr. Marek's analogy for 'starvation': "just enough food to survive", where 'food' can be either current or voltage being fed to the device. The term was coined during the hey days of valves (vacuum tubes)

The following two articles are in support.

1.  International Journal on Cybernetics & Informatics ( IJCI) Vol.2, No.1, February 2013

.   DESIGN OF A LINEAR AND WIDE RANGE CURRENT STARVED VOLTAGE CONTROLLED OSCILLATOR FOR PLL

Mr. Madhusudan Kulkarni  and Mr. Kalmeshwar N Hosur

2.3. Current Starved Ring VCO

These VCOs are made by using ring oscillator. The ring oscillator works by controlling the

charging and discharging of the gate capacitance of the next inverter. Decreasing the peak available charging current increases the time to charge and discharge the gate capacitance; consequently, the frequency is decreased Ring oscillators generate

high frequency up to 10 GHz.

Link:   http://airccse.org/journal/ijci/papers/2113ijci04.pdf

2.   WSEAS TRANSACTIONS on CIRCUITS AND SYSTEMS

         Current-Starved Pseudo-Floating Gate Amplifier

MEHDI AZADMEHR                                          YNGVAR BERG

                        Institute for Microsystems Technology

                                  Vestfold University College

                                   Raveien 197, 3184 Horten

                                                NORWAY

Abstract:

In this paper we present Current-Starved Pseudo-Floating Gate (CSPFG) inverters with capacitive feed-back. The analog CSPFG inverter suppresses low frequencies due to the active, local feedback. This inverter can be used in designing circuits and amplifiers where high frequency signal processing is the main goal. One good area of use is in filter design where a narrow band pass or reject filter is to be designed. Typical applications are detection of high frequency components in sensor signals, i.e. airbag sensors. AC simulation of the inverter is presented to show that the circuit is suited for high performance filter design. Linearity simulations of the analog

CSPFG inverters shows the good transient properties suited for amplifier design.

Key–Words:

Analog, CMOS, Floating gate, Inverter, Amplifier, Filter.

Link:   http://www.wseas.us/e-library/transactions/circuits/2008/25-728.pdf

P.S.

Thank you again for the last two replies.  And, yes - I know M. Blencowethes article "amplifiers under starved conditions". As far as I could see, in this article the "starved" conditions are realized using a kind of "bootstrapping".

I also know both articles given in the links provided in the last post. With the aim to clarify things let me quote the following sentence (airccs.org-link, below Fig.4):

"The current sources, M1 and M4, limit the current available to the transistor M2 and M3. In other words, the inverter is starved for current"

Does this really mean that both current sources (M1 and M4) are working with the minimum current possible? I don`t think so.  Of course, these "sources" provide/determine the current - but why are this "starved" conditions?

That is the core of my doubts and my question.

EDIT/UPDATE: There is another article "The starved-circuit amplifier" (J.D. Keith, Electronic Design, April 2, 2001). The amplifier consists of an npn/pnp combination and the "starved" collector current is app. 2.5 mA. This value is certainly not the absolute minimum for a workable transistor. Again my question: Why "starved"?  

Here are three other excerpts: 

1.) Thomas H. Lee: "The design of CMOS Radio-Frequency Integrated Circuits"

Adjusting the delay ring oscillator:

„....e.g by changing the load ...or varying the current drive of the inverters. One cheesy way to accomplish the latter is shown in Fig. 16-35 where a PMOS current mirror provides a limited , variable pull-up current to the CMOS inverter.

Caption to Fig. 16-35:  Simple current-starved CMOS inverter.“

2.) Another source states:

„One way to control the delay is to control the amount of current available to charge or discharge the capacitive load of each stage. This type of circuit is called a current starved inverter. „

3.) "For push–pull type elements such as inverters, the delay can be changed by changing the rate at which the output capacitance,CL, is charged. An adjustable current sink limits the peak current of an inverter and varies the delay, in other words the inverter is starved for current".

___________________________________________

To me, this sounds as if "current starving" simply means: To allow a certain (variable?) current maximum within a circuit.

UPDATE: If this "definition" (description) is true, the classical diff. amplifier with a current mirror load is also a "starved circuit", is it not?

.

A typical place you will find a current limit is on a bench top power supply.  The user can set the output voltage and the power supply will regulate the output voltage under varying current loads.  The user can also set the current limit to protect the load.  For example a power supply can output a constant voltage anywhere from 1 to 20V.  And it has the ability to supply up to 10A.  But the user can enter 2A for example as the current limit and 5V as the output voltage.  The power supply will output 5V for any current load up to 2A.  Above 2A the output voltage will decrease to a voltage that supplies 2A to the load.  The power supply has the ability to output 10A but by programming is limited to 2A in this example.

Current staving is slightly different.  Let's look at FET's IV curve with the gate set to a high enough voltage to fully turn on the FET.  For those who are not familiar with a FET's IV characteristics as the voltage between the drain and source increases the current increases linearly with a slope equal to 1/output impedance.  After a certain point the FET is supplying as much current as it can and the IV curve flattens out to slope = 0, say 20 mA  This is acting like a constant current source, as the voltage increases the current stays constant.  If this FET was used in a circuit that at times needed more than 20 mA the circuit would be starved for current.  The FET cannot supply any more current than 20 mA.

So the limiting case is the circuit and supply more current but is set to a lesser value.  The starved case is where the circuit cannot supply and more current because of the characteristics of the circuit.

Indeed, I-V curves of FETs show a flattened region. That's why some people call them "the transistor for those who love pentodes" (high input impedance, low dependence on supply voltage).

A pentode under starvation is often operated at unusually low screen grid voltages (a feature that FETs lack) and sometimes, low plate voltage too. However, FETs operating along the flattened region of their I-V curves are more commonly said to be in "saturation" by some authors, or in "active mode" by others. In their case, I'd stick to one of those designations instead.

Thank you again for all replies.

But the question remains: Is there really nobody who knows the DEFINITION of the term "starved" in this context? (For my opinion, B. Gilbert should know).

I would think that current limiting is done deliberately to get protection while current starving is due often to undesired conditions. let me explain. If I have a power supply capable of giving max 1 amp, I use current limiting (internally) to ensure that nobody can ever take out more than say 1.1 amp. This is a method of protection. [There are several situations in which current is limited deliberately to give protection for the equipment. One generally limits the current and if this situation continues, one may have some form of automatic shut off to get actual protection. many power supplies have this built in..and that makes them more robust.]

In contrast if I have a transistor with say a collector current of  100uA, at 25 degC and if the biasing is done so as to reduce the current as temperature is increased, one might expect a current of say 50ua at 65 degC, say the maximum temperature expected. But if temperature increases beyond that say to 90 degC, the transistor may end up in a current starved condition. the transistor may not operate in the intended fashion if the current is less than 50 ua, and we might use the term current starved to indicate this. Please do send me your thoughts.

I have seen some articles on current starved PLL at VHF and perhaps the explanation should address these. I regret I have not done that.

By Jane M Rabbey

The standard ring oscillator can be

modified into a VCO by replacing the standard inverter with a current-starved inverter. The mechanism for controlling the delay of each inverter is to limit the current available to discharge the load capacitance of the gate.