I've used Petri-Nets for the description of an audio processor. A Petri-Nets simulator is by way of example in Simplorer (ANSYS) implemented.
The best way to design a chip is to start with a Register-Transfer Level (RTL) description with Verilog or VHDL. Compilers exist for an automatic translation of RTL descriptions into a gate netlist.
If you are more interested in architectural design, you can start with a state-chart description (e.g., with Stateflow in MATAB). There are alos tools for translating state-charts into RTL or gate-level descriptions.
PETRI nets are useful (for my opinion!) only in very special cases for architectural design because most computer architectures are developed in the context of "signal flow (synchronous or asynchronous)" and "discrete events" , but not with the idea of a "token flow", which is the basis idea of PETRI nets. But, in controller design PETRI nets are sometimes used. State-charts seems to be the more natural to describe the actions in a new architecture.
Dear Peter, thank you for opening my question. This question is a result of another question:
https://www.researchgate.net/post/Do_you_think_that_the_Von_Neumann_Architecture_will_be_diminished_within_the_next_few_years_and_what_is_the_next_computer_architecture_as_you_see
In the future we have in human-machine-interfaces different architectures for audio signal processing, video signal processing and chemical structure analysis. For the inputs of these Micro- or Nanoprocessors we need not a Register-Transfer Level (RTL). We have as input only integrated converter for one- or multidimensional data streams. Also we need not a clock-synchronization. These Micro- or Nanoprocessors work with innate asynchrony clock, normally event driven. The output will be success over a data bus-system. At least the RTL is for development ancillary.
Primary for development is the structure of PETRI nets. In my “Procedure of contemporary ascertain for characteristic value, harmonics and non-harmonics of quickly alterable signals” I have used seven levels. Each level contains a PETRI net with exactly one marking. See the link
https://www.researchgate.net/publication/235222986_Verfahren_zum_zeitnahen_Ermitteln_der_Kennwerte_Harmonischen_und_Nichtharmonischen_von_schnell_vernderlichen_Signalen
For better understand my development language: Every PETRI net consists of states, events and actions (compare with SML code of Simplorer). On every level of PETRI nets is only one state marking.
Regard Christian
Patent Verfahren zum zeitnahen Ermitteln der Kennwerte, Harmonische...
If you want to build a processor in very low level, the suitable languages are VHDL or verilog. If you are ready to build the system using high level languages, the suitable one is bluespec, system C, impulse C and Handle C
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