I temporarily leave the “kingdom” of my favorite analog electronics and move to the neighboring field of digital electronics because this term I will conduct a series of labs in the laboratory on digital circuits. I do it since I want to be helpful to my students (both useful and fun) secretly hoping they will join my web initiative in return. Of course, I will not waste their and your time with banal, trite and boring book explanations; instead I will “provoke” readers with unusual, extraordinary and sometimes weird viewpoints with only the purpose to make them not only know but think and understand digital circuits...
For quite a long time I have discovered that there is a close connection between the input parts of the transistor-transistor logic (TTL), diode-transistor logic (DTL) and diode logic (DL). Thus TTL includes DTL... and DTL includes DL... or DL have evolved to DTL... and then DTL evolved to TTL... So, it seems to understand what TTL is, we have first to understand what DL is... to unveil the mystery about it. I did it yesterday together with my students by reinventing the circuit to ask all these questions:
"Why were the diodes back to front? Why was the resistor connected to +V instead to the ground? Why was there no input current when the input voltage was high? And why was there input current when the input voltage was low? But why did the current go out of the diodes and went in the input source? Why was it impossible to make inverting diode gate? Why was AND gate supplied by an additional voltage source while OR gate had no such a source?.
In logic gates, logic functions are performed by parallel (OR function) or series (AND function) connected switches that are electrically controlled by the input logical variables. Diode-based logic gates (DL, DTL and TTL) are implemented by diode switches (when forward biased, a diode is “closed”; when backward biased, it is “open”). The paradox of the diode logic is that diode AND logic gates should be implemented by series connected diode switches (like an NMOS AND gate implemented by series connected transistor switches)... but still it is implemented by parallel connected switches. Why? Here is my explanation.
In contrast to transistors, diodes are odd two-terminal switching elements, in which the input and output are not separated; they are the same. So, series connected diode switches cannot be driven by grounded input voltage sources. To solve this problem, diode AND gates may be constructed in the same manner as OR diode gates - by parallel connected diode switches. But to obtain AND instead of OR function, according to De Morgan's laws, the input (X) and output (Y) logical variables should be inverted:
Y = NOT (NOT (X1) OR NOT (X2)) = NOT (NOT (X1 AND X2)) = X1 AND X2
So, the diode AND logic gate is a modified diode OR logic gate: the diode AND gate is actually a diode OR gate with inverted inputs and output. Let’s see how it is implemented in the ubiquitous circuit (see the attachment).
To realize the clever De Morgan's idea, the diodes are reverse connected and forward biased by an additional voltage source +V (the power supply 2) through the “pull-up” resistor R1. The input voltage sources are connected in opposite direction to the supplying voltage source (traveling along the loop +V - R1 - D - Vin). To invert the output voltage and to get a grounded output, the complementary voltage drop (+V - VR1) between the output and ground is taken as an output instead the floating voltage drop VR1 across the resistor.
Input logical “1”: When all the input voltages are high, they "neutralize" the biasing supply voltage +V. The voltage drops across the diodes are zero and these diode switches are “open”. The output voltage is high (output logical 1) since no current flows through the resistor and there is no voltage drop across it. So, the behavior of the diode switches is reversed - whereas in diode OR logic gates diodes act as normally open switches, in diode AND logic gates diodes act as normally closed switches.
Input logical “0”: If the voltage of some input voltage source is low, the power supply passes current through the resistor, diode and the input source. The diode is forward biased (the diode switch is “closed”) and the output voltage drop across the diode is low (output logical 0). The rest of diodes connected to high input voltages (input logical “1”s) are backward biased and their input sources are disconnected from the output 1.
I exposed my speculations, two years ago, in the Wikipedia page about diode logic (under the name Circuit dreamer):
https://en.wikipedia.org/wiki/Talk:Diode_logic#Revealing_the_secret_of_diode_AND_logic_gate
https://en.wikipedia.org/w/index.php?title=Diode_logic&oldid=445500585#AND_logic_gate
Dear Dr. Cyril Mechkov, you explained your question very well and in depth. Your confidence in analog will surely lead to the height of digital electronics. I will soon coordinate with you on some topics of digital system testing.
Prof. Subramanyam, everybody starts with diode logic but nobody shows the evolution of DL to TTL:)
Transistor (transform of resister) can be considered as back to back diodes .NOT operation can done easily .Diodes are more suitable for AND and OR.
Bhupendra, but note that both the diode logic gates (OR and AND) are implemented with parallel connected diodes...
This week, I used the building "scenario" above to show to my students the AND gate evolution from the humble diode logic (DL)... through the diode-transistor logic (DTL)... to the transistor-transistor logic (TTL). They listened to me with interest and the brightest of them (Lubomir from group 51; Hristo and Nikola from group 50; Stoyan, Rumen and Miroslav from group 52) participated in this reinvention of the legendary gates... I hope that some of them will add their impressions and own comments (through my account) to help this sluggish discussion...
Initially, my students were surprised by the strange and counterintuitive behavior of TTL gates:
1. They knew when connecting a positive voltage source to a load (with the purpose to apply an input logical “1”), a current should flow from the source to the load ... however, in this case, any current did not flow... but the gate still took this input signal as a logical “1”...
2. Then, they knew if they leaved the input unconnected thinking that so they applied an input logical “0”, of course the current should not flow... and it did not flow... but the gate continued taking this input signal as a logical “1”...
3. And finally, they expected if they shorted the input to (really) apply an input logical “0”, no any current to flow (there was no voltage, so there was no current)... but still a current flowed... and imagine it even flowed in the opposite direction (from the load to the source)! What a magic! Everything was turned upside down!
But then, after revealing the secret of diode and diode-transistor logic, they understood why TTL gates behaved so strange and unusual...
I appreciate this approach... but wikipedians - not:
https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic
Can you include a reference to this reputable source in the Wikipedia page?
I forgot to say that the section “Transistor-Transistor Logic (TTL)” is from 4th edition of Sedra/Smith’s “Microelectronic Circuits” (see also attached file):
Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 4th ed., Oxford University Press, 1998.
This section is not included in newer editions of this textbook:
Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, Fifth Edition, Oxford University Press, 2003.
Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 6th edition, Oxford University Press, 2009.
Prof Nebi Caka, thank you for the excellent suggestions! The Sedra&Smith's book is just wonderful (it reminds me, as a style, the Floid&Buchla Fundamentals of analog circuits but it is better). I would be thankful if you attach the previous chapter about diode and diode-transistor logic.
This morning, I printed the pages about TTL, take them with me and went to my favorite park near the University. I stretched out on the grass, began to bake under the sun and reading all these wisdoms. Young people around me (maybe some of them - my students) were playing ball and cards, walking dogs, drinking beer, flirting... but I was pondering on the mysteries of these great circuits...
I remembered my teacher on the subject of Digital Circuits from the late 70's (his name was Dimitriev; he was married to a German, and when the "wind of change" began to blow in Bulgaria, he emigrated to Germany). It is interesting that he tried to show the evolution of diode-transistor logic (DTL) gates into transistor-transistor logic (TTL) gates in the same manner as S&S. But what is more interesting, I (about 23-year-old young man) had no interest and was even a little irritated from these lengthy explanations:) And what is most interesting is that now, after more than 30 years, I try to do the same with my students... and maybe they are bored like me then:)
Well, now about the S&S bestseller (compared with the H&H bestseller)... Yes, it is perfect, great, it is what a "standard" ordinary student would desire... it is like a "bible" in the field of electronics... but I need something more... It presents "ready-made" circuit solutions in a free and unconstrained style saying HOW IT IS MADE... but I need to know WHY IT IS MADE EXACTLY IN THIS WAY... because science, engineering, education, technical education, electronics, circuitry... are not religion... Maybe, looking from this perspective, I prefer to read H&H bestseller since it excites my imagination...
Hey guys, to really find an answer to why they did the things they did, you have to TELEPORT yourself to 60's and 70's :) Let's do that :)
First of all, Cyril, you are leaving a very important question out: When you are designing a logic gate, two things are important : 1) Logic function, which you covered very well, 2) DRIVE CAPABILITY, i.e., FAN OUT
Ok, Cyril, let me put you back into your natural KINGDOM : ) In nowhere in this discussion, you brought up FAN OUT, which makes a giant difference when you are designing the gates.
LET'S GET ANALOG :)
*** In the very original circuit, you described an AND gate with a very good SINK capability, and terrible SOURCE capability. To improve its SOURCE capability, you need to make R1 real low, which makes the power consumption terrible !
*** In the second circuit, you described an OR gate with a good SOURCE capability, and bad SINK capability ... Same story.
In IC design, there is a concept called FO4 delay (fanout-of-4), which is the delay when an inverter is driving four identical inverters ... We make extreme effort to make sure that, gates have SYMMETIC rise/fall times, which is directly related to the pull-up resistance, vs. pull-down resistance. In your case, obviously, pull-up and pull-down resistances are way out of alignment. Not your fault, nature of the beast (i.e., DL).
So, functionally, these will work, but, the delays are ... god knows :)
The fanout is an extremely important point, which was pretty much irrelevant in the DL technology, since you have such an uneven sink/source capabilities. In other words, you are providing a WEAK 1, and a STRONG 0, or vice versa ...
This wasn't even the bad news. Here comes the bad news: The WEAK 0 (or WEAK 1) problem gets compounded, i.e., it gets worse with every stage. In other words, WEAK 1 gets weaker, weaker ... OF course, a WEAK 1 followed with a 0 goes back to normal. So, the operation of DL is very data dependent ... In other words, since there is no AMPLIFICATION (like with a transistor), there is a limit on how many of these guys you can cascade before you can't even guarantee correct operation ...
Dear Professor Cyril Mechkov, I am following this question and learning alot. Thank you for initiating, providing and sharing information & knowledge in deep insight. Thank you very much for this gesture.
Tolga, really I and my students "TELEPORT ourselves to 60's and 70's" when discussing famous logic gates:)
My goal in this question was to reveal how abstract logic functions were implemented in digital electronics. But your remarks about FAN OUT are very relevant here; they can act as a prelude to the next questions about transistorized logic gates. Thanks for your interesting thoughts.
https://en.wikipedia.org/wiki/Diode_logic#Non-restoring_logic
Regards, Cyril
It is interesting to see why the diode logic is non-inverting in both the OR and AND configurations: a diode OR gate is true non-inverting (Y = X in the case of one-input OR gate)...
... while a diode AND gate is non-inverting since it is double inverting (Y = NOT (NOT (X)) = X in the case of one-input AND gate - see the considerations above in the question body.
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