Can any one tell is the Synopsys physical compiler tool is available to the University customers? What are the advantages of using Physical Compiler over Design compiler in logic synthesis phase?
Dear Dr Sivanantham,
the advantages may be as follows
-Advanced optimizations deliver 10% faster timing QoR
-Physical guidance to IC Compiler tightens correlation of timing, area and power to within 5% and speeds placement by 1.5X
-Accurate pre- and post-synthesis congestion prediction and congestion-driven optimization eases routing
-Gate-to-gate optimization for smaller area on new or legacy designs while maintaining timing Quality of Results (QoR)
-Cross-probing between RTL, and design views such as schematic, timing reports and physical views for faster debugging
-Early physical visualization and debugging identifies layout issues prior to physical implementation
-Floorplan exploration for faster design convergence to an optimal floorplan
-2X faster runtime on quad-core compute servers
-Concurrent multi-corner, multi-mode (MCMM) synthesis.
i am attaching a book also.it might help you.
thank you
http://www.synopsys.com/tools/implementation/rtlsynthesis/dcgraphical/Pages/default.aspx
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