It might be surprising, but the layout of a NAND gate in finFET technology (and most other simple gates) looks remarkably similar to that of the gate in planar technologies. Of course the active device region is made up of distinct fins, and the real FET topology is quite different. But from a layout point of view, you'll have the same gate shapes, source and drain contacts, metal straps, etc. If you ignore the shapes of the fins, it all looks quite "normal". Of course the fine details will depend on the technology ground rules that you are working width. Also, the finFET technology gives you the opportunity to grow the device widths (compared to the planar structure) in the same footprint.

I thought the same hypothesis, but I would be interested to know if there are some standard gate-to-gate spacing dimensions for the FinFET technology.

Thanks in advance

The gate-to-gate spacings will typically be scaled in the regular way, from the previous generation technology. Even though the gate topography makes processing more difficult, it's probably best to assume that gate-to-gate spacings will just scale with the base lithographic dimension.

Do you know a reference (publications) to find a top-view picture of the layout of simple gates (NAND, NOR, XOR) in FinFET technology in Bulk or SOI ?

You could find some layouts using different finFET device topologies, in Alioto's work, IEEE Trans VLSI Systems, vol 19 No 5, p. 751 (2011). I also have described some of the generic issues in a conference presentation I gave recently. Here is a link to those charts:

https://www.researchgate.net/publication/238732221_J_Warnock_ISPD_2013_14nm_Slide_deck?ev=prf_pub

Data J Warnock ISPD 2013 14nm Slide deck

Thanks for the both references, it's exactly what I need. If you are interested, I could keep you informed of my work of soft error estimation based on these FinFET layout.

Sure. I'd be interested to hear what you find.

i've published a first paper about the transient charge collection induced by energetic particles in sub-100 nm SOI FinFET technologies with the aim of estimating the SEU (Single Event Upset) and MBU (Multiple Event Upset) sensitivities.

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6532108&queryText%3DL.+Artola

Let me know if you have some questions or remarks about it

I will present at ESREF Conference (September 30th-October 2nd), my work titled "Comparative SET evaluation of Layout cells in FinFET technology".

This work presents a comparative soft error evaluation of logic cells in FinFET technology. This work leads to characterize a gate library (NAND, NOR gates) with the aim to identify critical are of the design and help designer to minimize the soft error occurrence. The modeling platform called MUSCA SEP3 is based on multi-physical approach and electrical simulations. Single Event Transients induced by radiations are modeled taken into account the layout properties and the electrical characteristics. Good agreements between the calculated transient currents and TCAD Mixed-Mode simulations are demonstrated. The impact of drive strength and core voltage is presented and discussed.

New works about the soft error sensitivity of majority VOTER design in 7nm FinFET technology have been published and will be presented next week at the 2017 ESREF conference in Bordeaux, France.

Radiation-induced soft error is an ever-increasing concern in the microelectronic industry in order to provide reliable VLSI systems at advanced technology nodes. Most of the redundancy-based methodologies adopt majority voters to ensure the fault masking. This paper presents a comparative analysis of different majority voter designs in 7 nm FinFET under radiation effects. The MUSCA SEP3 tool is used to estimate the SER of each circuit. Results show that NOR voter is less sensitive than the NAND voter. However, the SET pulse width is larger for the NOR voter than NAND voter.

You could find more details there:

https://www.researchgate.net/publication/318034774_Evaluation_of_Radiation-Induced_Soft_Error_in_Majority_Voters_Designed_in_7_nm_FinFET_Technology

Regards

Laurent ARTOLA

Article Evaluation of Radiation-Induced Soft Error in Majority Voter...