Dear Vidhya,

Your question can be answered both from a technology level and at circuit level perspective. I presume your question concerns mainly the latter.

At circuit level, the threshold voltage can be reduced by increasing the potential of the channel for the same gate-source voltage. As the channel potential is the result of the gate, source, drain and bulk/body (back-gate) potential, playing with the latter three can effectively alter the threshold voltage.

Apart from the gate, the terminal that has the largest effect on the channel potential is the bulk. This is particularly true for transistors with a relatively long channel and/or a thicker gate oxide. It is for this reason that you will find quite some examples of circuits that employ bulk/body biasing to lower the threshold voltage of circuits in the open literature. Increasing the bulk-source voltage (assuming an NMOS device) effectively reduces the needed gate-source voltage to accomplish the same drain current. Be aware though that increasing the bulk-source voltage will forward bias the bulk-source PN junction and thus may require additional current.

In principle, the effective threshold voltage can also be lowered by playing with the drain voltage, as this terminal also has an effect on the potential in the channel. This may be an interesting technique for short-channel transistors in deep submicron technology or even for the recently introduced FINFETS, by employing cascode techniques. However, I presume you wish to reduce the threshold voltage in order to allow for smaller supply voltages. In that case, there will be no room for cascode (stacking) techniques altogether.

If you wish to learn more about the operation of MOS transistors and the effects of the various terminal voltages on the threshold voltage, I can recommend papers by Christian Enz on the so-called EKV MOS transistor model. One I particulalrly like and use is the one from 1995 in Analog Integrated Circuits and Signal Processing (Kluwer Academic Publishers).

I wish you success!

Wouter Serdijn

Some TECHNOLOGY LIBRARIES (e.g., 130nm IBM) contain two different type NMOS and PMOS transistors: Low-Vt, and High-Vt. They are also symbolized slightly differently, with a thicker gate symbol etc ... So, the designer uses low-Vt transistors wherever the PERFORMANCE is critical, for example, on the critical paths of the circuit. And, the designer uses the high-Vt transistors wherever PERFORMANCE IS NOT critical, but, rather the power consumption is ... High-Vt transistors are slower, but, they have much less LEAKAGE, thereby reducing the power consumption significantly. Alternatively, low-Vt transistors can be up to an order-of-magnitude faster, at the expense of order-of-magnitude higher leakage.

This design technique is increasingly more important as the technology node scales down (e.g., 32nm.) since the leakage is a bigger and bigger problem at the lower technology nodes. For example, a 32nm.-based INTEL CPU's power consumption is almost 40-50% due to LEAKAGE, requiring sleep transistors to activate/deactivate parts of the chip, whereas, for example, at the 0.5 um technology node, leakage was barely even studied as a relevant concept.

The threshold voltage can be reduced by reducing the oxide thickness and by reducing the channel length(short channel effect) threshold voltage is reduced.and by increasing the body and drain voltage we can also reduce the threshold voltage.

Hello Gagandeep Singh

Can you please give me the technical explanation about threshold voltage reduces by increasing body voltage?

Let take an Nmos. The body is a p Substrate and the source is n-type. When both source and body are grounded the source and body junction region is reverse biased and there is no flow of electrons from source to body. By increasing the body voltage we are forward biasing the source and body region, as a result, electrons start moving toward the body and eventually break the barrier and occupy the holes in the body. Threshold voltage depends on the hole concentration in the body. As the hole concentration is reducing because of the forward bias threshold voltage reduces.

The threshold voltage of MOS transistors is mainly controlled by adjusting the thickness of the oxide, and by ion implantation of the suitable doping atoms for both n and p channel transistors.

The bulk biasing is used to normally to increase the threshold voltage since one has to apply only reverse bias on the backgate since forward biasing may lead to substrate current. which is not acceptable.

For more information about the threshold voltage adjustment, please refer to the book: Book Electronic Devices

Best wishes

by reduce thickness of the oxide

Hi Vidhu! Perhaps you can try using floating gate approach where you add capacitors prior to the gate electrode and one of the capacitors you add is connected to a certain bias voltage which tends to reduce the effective VTH of the MOS. I tried it and it seems to work. All the best!