I ma trying to design a layout file (.gds) for a silicon Photonics Integrated circuit that can be sent to fabrication, but I am wondering with the tool to be used. Since, I am just a beginner, all the tools looks same. So, I would like to know whether I should choose some expensive tools or just using K-layout can also lead to same output as of other tools. What are its pros and cons?
What are the differences between those tools and what are the key factors to be considered while choosing the right tool?
Hi Bishal,
Your design tools and environment will be determined by the process you choose to fabricate your chip by.
The paid tools you mentioned (Phoenix, Cadence, etc.) are not simply just layout tools, they are a complete EDA package. They work with circuit simulation tools to enable schematic-to-layout and enable DRC checking. Typically, commercial foundries provide PDKs for their processes in these tools.
On the other hand, kLayout is mainly a GDS Viewer with very limited design capabilities. The bare bones version can only draw primitive shapes. HOWEVER... several contributors (mainly UBC lab and Princeton Lightwave lab) have invested significant efforts in advancing the capabilities of this tools by introducing the SiEPIC-Tools and the SiEPIC_EBeam_PDK, which are available as free packages in kLayout. The SiEPIC package works with Lumerical EDA tools to enable all the above functionalities and in addition, very advanced functionalities which are lacking in many of the commercial tools above such as functional layout check. Feel free to dig into our GitHub repositories or ask further questions if you are interested.
Cheers,
Mustafa
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