I'm trying to guess what are L1 caches typical pipeline stages. The attached file describes a 3-cycle one, like those found in Silvermont, Jaguar, and Cortex-A9. The notation conventions are:
- blue for the adress computation;
- yellow for the adress translation;
- orange for the data access.
However, high-end CPUs such as Haswell, Bulldozer, and Cortex-A15 have a 4-cycle L1 cache access latency. Where does the fourth cycle come from? Could someone explain in detail what do the four stages do?
Pipeline stages are not really related to caches. You can have more stages in the instruction pipeline of a CPU - fetch instructiion, decode instruction, compute address of operand1, fetch operand1, compute address of operand 2, fetch operand 2, execute instruction, ...
Caches store the instructions and data for the CPU so that these steps can happen at a very high speed.
@C.P. Ravikumar : That's not my question. I wanted to know what do the four pipeline stages – dedicated to cache access – do in detail (known as EXE, DC1, DC2 and DC3).
It can be seen from the picture that the fourth cycle is for Write Back. I cannot tell for sure without "the whole picture" (you attached only the picture for the L1 pipeline stages), but the write is not necessary if you only read from the cache, for example when you use the cache in the instruction fetch stage, or when you have instructions that read from the memory (like Load). If, on the other hand, you have instructions like Store, which writes to the memory, than that fourth cycle is spent for the write. Again, I am not sure this answer is complete (or at all correct), but I hope I helped you a little bit...
@Nikolaos Alachiotis: Write-back is not taken into account in the four stages.
@Vladimir Stankovic: Write-back is not taken into account in the four cycles. Moreover, these stages correspond to load accesses.
Hm... I'm confused... First of all, the fourth cycle IS dedicated to the write back - as shown in the picture (the 1st cycle is for EXE, the 2nd and 3rd for DC1 and DC2 respectively, and the 4th for the write-back). But I don't understand the purpose of the write-back. In case of a TLB miss, the new item is read from the next level of cache/memory, and then written back into the TLB, but I am not sure that it can be all done in a couple of cycles (the TLB read in the 2nd cycle and the write back in the 4th cycle)...
During the write-back (denoted as WB) stage, datas are driven to the register file and the forwarding logic.
TLB misses are handled by a L2 TLB in high-end CPUs. The miss penalty is 8 cycles in Haswell.
If the write-back is for the register file, then it indeed is not part of the L1 pipeline stage. I misunderstood your question, sorry... You attached a file for a 3-cycle L1 cache, and ask about the 4-cycle caches, for which you don't have a figure. I was trying to give a logical explanation, based on my general knowledge, and you obviously need someone with knowledge about this specific question. Hope you find someone... I can continue with "loud thinking" about the possible answers, if you think that might be helpful to find out the answer?
As I said, write-back is not taken into account in the four cycles. It is shown for information purposes only.
Low-end CPUs – such as Silvermont – have a 3-cycle data cache pipeline (c.f. my picture: EXE, DC1 and DC2). High-end CPUs have a 4-cycle one (EXE, DC1, DC2, DC3). My question is: why four cycles?
I can only wild-guess... It could be that high-end CPUs cannot do all the necessary "work" in just 3 cycles, due to their operating frequency, so they need one more cycle. Therefore, DC1, DC2 and DC3 in high-end CPUs do exactly the same as DC1 and DC2 in low-end CPUs, only in 3 cycles instead of 2. But that is just a thought, I have no idea if that is true. You did not answer me - do you want me (and the other people here) to write our thoughts about what could be the answer or you specifically ask if someone knows for sure the answer to your question.
Hi Hugo,
Did you find the answer to that question? I am also interested on it.
Also, in your picture I can see that the cache miss/hit is know in the last stage (cycle 3). Do you know if in a 4-cycle pipelined cache the miss/hit info is obtained in the last stage?
Thanks,
Alberto
The diagram I attached seems to represent the typical pipeline of an L1 cache. A fourth cycle can be added because of:
– the presence of multiplexing/demultiplexing circuits in a multibank cache;
– the absence of load-hit speculation, which would explain why the load latency in the Intel's cores is 4-5 cycles (c.f. 7-cpu.com), although this seems unlikely.
The addition of a fourth cycle does not necessarily implies delaying the hit/miss information.
In the book by Antonio González et al. "Processor Microarchitecture: An implementation perspective", Chapter 2, they mention the 4 states of a pipelined cache: Address calculation, disambiguation (decoder), cache access (parallel tag and data), and result drive (aligner).
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