Some general suggestions:

- Use tight slew control on all clock nets

- Do not use small inverters or buffers, which are subject to more variability

- Use wide wires, shielded if possible to cut down on noise and variability

- Do not use a mix of threshold voltages or different channel lengths: use one common device type for all gates

- You may want to pre-route certain trunk nets or some sections for better results

- try to minimize overall latency

In general you will find that there are some tradeoffs between power and skew (lowest-skew solutions are likely to have higher power disipation

Thats really helpfull. Thanks a lot

How does Useful skew driven H-trees work in CTS performance?