Should the static power obtained from DC be the same as obtained from a transient analysis? In case of aysnchronous CMOS, how do you determine the static leakage in a tool, say eldo?
Dear Kashif,
The power consumption of any digital circuit is the sum of the static Ps and dynamic losses Pd. The dynamic power loss is the switching losses in the change of conduction state.from the off to on and from on to off state; that is turn on and turn off losses.
So, Pd= Pon + Poff,
The static power loss is the power loss in the on steady state and in the off steady state as a leakage power.
So, the Ps= Psson +P ssoff
In the CMOS gates the transistors act as switches and ideally their off power is ideally zero. However, the short channel scaled down transistor has an appreciable off leakage current that can not be neglected.
It is so when you apply square wave input to an inverted for example and its pulse width is sufficiently greater than the on and the off times, the output voltage settles to steady state values where the state of the transistors can be considered quasi static and consequently by measuring the voltage and the current waveform of any transistor at the off state one can calculate the tle leafage off power.
It is expressed by Pssoff= Voff x Ioff.= integral of V(t) I(t) dt/ Toff, where Toff is the off time
In this way you can calculate the leakage power for all the transistors in the circuit.
If all the transistors in the circuit are made off, then you can measure the off leakage current by the power withdrawn from the power suppl VDD
So, generally, in order to measure the leakage losses the transistor must be in the off state.
Best wishes.
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