Most of the device modeling for nanoscale MOSFET where degenerate doping of the substrate is a must, assumes that although there is incomplete ionization at lower substrate temperature than 300 K but at room temperature, doping ionization is 100%. This modeling practice has provided erroneous results for MOSFET device performance simulation where substrate doping is essential modeling parameter. I am attaching the following papers for reference. I would like the readers to concentrate on Figure 6 of the first paper attached. Here with increased doping level from 10^17/cm^3 to 3x10^18/cm^3, the ionization ratio gradually decreases to to about >0.75 and then rises again to unity close to 10^20/cm^3. Since the source and drain regions of all nanoscale MOSFET are doped of the order of 10^20/cm^3 to 10^21/cm^3, it looks like the source dopants are more or less ionized close to 100% but the substrate for example junctionless FET where very high degenerate doping level of the order of high 10^18/cm^3 is required, Figure 6 of the first paper attached shows that ionization will be in the vicinity of 0.8 or 80% even at room temperature. Band gap narrowing which is dependent on degenerate doping levels, need to be remodeled where the continuous variation of dopant ionization values for high degenerate doping levels need to be properly estimated through analytical means that replicate Figure 6 for n-type substrate (first attached paper) or Figure 5 for p-type substrate (second attached paper). Similar ionization curve for p-substrate can be found from the second attached paper. Intrinsic carrier concentration for silicon at T = 300 K rises from its actually quoted value when due to degenerate doping, energy band gap narrowing takes place. Model equations are available to quantify this narrowed band gap with respect to substrate doping values, albeit assuming complete ionization. But as we see < 10^20/cm^3 doping levels, ionization ratio is between 0.8 and 0.9 or 80%-90% and this feature needs to be included in an analytical derivation format just like Figure 6 of the first paper attached or Figure 5 of the second paper attached. Once the ionization is precisely defined, the different band gap narrowing models can be computed to extract intrinsic carrier concentration value for silicon at T = 300 K when it sharply increases from its quoted value. Not accounting for this incomplete ionization of degenerately doped substrate value, most of the modeling calculations including high doping value dependent intrinsic carrier concentration at T = 300 K for Silicon FET will be error prone. I am still not sure Silvaco modeling library provides the users the analytical equations that precisely provide the total ionization at T = 300 K for degenerate donor or acceptor dopants as per Figure 6 of first attached paper or Figure 5 of the second attached paper.
I initiate this discussion related conversation here based on the above contents shared with Research gate community.
Sincerely,
Dr. Nabil Shovon Ashraf
Associate Professor
Department of ECE
North South University
Dhaka, Bangladesh.