I have a LSMO/STO film. I am working in the 2 probe geometry and applying a gate voltage at the back of the STO substrate. I am seeing a very peculiar behavior in the drain source voltage. For a source current of 1uA the voltage drop at the two probe shows a voltage of 25 mV, now as soon as I apply a back gate voltage of -110 V the 2 probe voltage drops from 25 mV to -0.3 V. Should the 2 probe voltage be negative on applied gate. However if we apply a higher source current (0.5 mA) the two probe voltage drops but remains positive on applying a gate voltage of -110 V. Thank you in advance
Thank you Michael Uebel for suggesting me these papers. However I could not find a solution to my problem. Let me rephrase my question again: While I apply a back gate voltage, the gate-source (V_gs) terminal comes out to be at a higher potential than the gate-drain (V_gd) potential, as a result of which a current appears to flow between the drain-source terminal (the drain source voltage is off). For eg. At a gate voltage of -110 V, V_gs=-110V whereas, V_gd=-106 V. As a result of this offset, I get a drain-source voltage even when the drain source terminal is not biased. I am not able to understand why this offset is appearing, could it be due to the leakage current?
And also this offset increases for higher gate voltages , at small voltages eg 2V this offset is not present
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