I would like to perform a tolerance analysis of a CLLC topology using matlab simulink. But the main constraint is the simulation speed. It takes almost 20mins to perform one simulation . The switching frequency of the model is 200KHz. The simulation step size is 1e-8. I am currently using the circuit simulation model. i would like to perform some 2000 simulations using monte carlo approach. This can cost me more time. Is there any better solution available?
Hello Suresh Rajaram ,
I don't know which type of MatLab/Simulink you are using: 1) student, or 2) professional, and I don't know the hardware you are using, but one way around your problem is to lease space on a very fast computer like a windows PC with an i9 processor, or the latest Apple computer. When you lease space on a remote machine you are given a partition on the hard disk drive or solid state drive in which you can store your application programs and your data files; I am not sure whether you can ask to be the only user on the leased machine. If you have the professional version of MatLab/Simulink, you will have to contact MathWorks to find out the procedure for moving the application from one machine to another and back, again, to the original machine so that you do not exceed the terms of your license (number of seats).
Regards,
Tom Cuff
Thomas Cuff ,
Thanks for the feedback. I am using a professional version of matlab. As you suggested one way is to solve this problem by using a high end PC. But I cannot afford such cost. Is there a way to solve this in the model itself by following a different modeling approach? I have seen an average modeling approach (also known as large signal model) . This doesn't uses the PWM rather it uses only the duty cycle. It only captures the average effect. That is ok for me. But i don't have much experience so i would like to know if anyone has tried this approach before for the tolerance analysis.
Hi Suresh Rajaram ,
I would have thought that large signal analysis would be slower than small signal analysis. Normally, when your circuit contains semiconductor devices, the characteristic curves of these devices are nonlinear. If you bias these devices about some operating point, the small signal behavior will be linear about the operating (bias) point, and the simulation will converge rapidly. However, if you bias the devices and apply a large signal, then the behavior may be nonlinear and the solution will usually converge at a slower rate, and the solution may not be unique; a linear solution is guaranteed to be unique.
Is your tolerance analysis simply looking at the effects of piece part variability and/or operating temperature? Don't forget that there is additional variability introduced into the circuit during its fabrication process. For example, suppose you are using surface mount components, where solder paste is applied first to the pads of the PCB (Printed Circuit Board), then a pick-and-place machine installs the components, and finally the panel is run through a reflow oven. Depending on the temperature of the panel in the reflow oven, tolerances of the parts may permanently shift. Usually, because the circuit boards are so small, there are multiple PCBs on a single panel, and each PCB is surrounded by stress relief notches. In the depaneling process, the individual PCBs are mechanically cut from the panel. The depaneling process can flex the PCB enough to crack surface mount components, which can lead to higher infant mortality.
Regards,
Tom Cuff
The easiest tolerance analysis, of which I've used, is Micro-Cap, a SPICE program. Micro-Cap can perform worst case by varying every component to the max and min levels. https://www.spectrum-soft.com/download/download.shtm