I have simulated my verilog code and verified it on simulator as well as FPGA.
Now I have sythesized that verilog code into Cadence RC .
I have done the functional verification using NC SIM.
But now how do I simulate the sythesized code for timing verification by attaching the 65nm standard cell library ?
Is there a way to do this in virtuoso or any other tool inside cadence ?
Also I have done RTL to GDSII in Cadence SoC encounter and have a gds file ready . Now is there a way to simulate this gds file in virtuoso ? I am able to import this gds file into virtuoso but is there a way to simulate this gds file ?
As the result of logic synthesis you can obtain:
To simulate the design you need:
To simulate the design use the NC Sim as usual but replace the DUT model with the netlist and add to the project Verilog description of the technology library. In order to utilize the SDF timing data you need to configure back annotation procedure which is part of elaborator configuration.
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