Omkar Pujari

4 Questions 2 Answers 0 Followers

Questions related from Omkar Pujari

Can someone suggest few papers on clock domain crossing which are VERIFIED AND TESTED ON FPGA ?

I am working on one of the paper on clock domain crossing. I am searching relevant papers which are tested as a proof of concept on FPGA. There are papers which talk of RTL Simulation but I am...

15 April 2016 210 5 View

Is there a way to create timing simulation for the netlist generated from Cadence RC just to verify that the timing is satisfied for 65nm library?

I have simulated my verilog code and verified it on simulator as well as FPGA. Now I have sythesized that verilog code into Cadence RC . I have done the functional verification using NC SIM. But...

01 January 2016 3,966 1 View

Is anyone working on Intel Galileo board?

I am working on a project but I am stuck in the middle while working on Intel Galileo gen2 .I am using the mraa library on python which is available in the iotdk yocto image . I am able to read...

16 May 2015 1,837 0 View

We bias nmos and pmos in a real chip by using current mirror. But how do we design the reference current source in a IC?

I am designing a CS Amplifier in CADENCE Virtuoso with 2 nmos and 2pmos.The lower nmos is used for amplification and the upper nmos for casoding.The upper 2 pmos are used for current source and...

30 March 2015 1,937 5 View