I had maken a simple MOSCAP by sufficiently depositing Al and Ti/Au on SiO2(100nm)/p-type Si wafer. However, the electrode area is significantly large(4cm^2, square), compared to typical cases. Bias and ac signals were applied through a probe station, and measurements were taken with an LCR meter.

However, regardless of the gate electrode material, I could not obtain a proper C-V curve in the low-frequency range (20~100Hz). The capacitance value was excessively small compared to the ideal value across all bias regions. Additionally, the capacitance in the inversion region did not rise to C_ox. I think this phenomena can be explained with "deep depletion", and I believe it is due to the influence of the large capacitance (~140nF).

I made a simple contact to the bottom silicon bulk using a diamond pen, silver paste, and copper wire, and performed open and short corrections correctly. Compared to the ideal results from a small-area MOSCAP, these experimental results, which do not match theory, are quite confusing to me. However, increasing the contact area at the bottom tends to increase the capacitance.

Is there anyone who could share their wisdom with me?