It doesn't.

I would argue you don't need it. Your RTL code is probably behavioural, other than some module definitions and the hierarchy of those modules, it is far from being a netlist-like schematic.

Maybe what you want is a synthesis tool.

So far, I do not find RTL schematic design feature is available in icarus verilog. Since you already did a simulation from the code, you can still verify functionally your works. Unless you need the schematic so much, a synthesizer tool is needed.