Dear Renish,

You measure the quantities as you define them. This is a measuring concept. So, i would advise you to define the leakage current of the NAND gate. 

From the conceptual point of view, The leakage current is defined for an off transistor or an off switch. If the the transistor is stressed by VDD and its off leakage current is IL, then its leakage power will be VDD IL. In case of NAND, the leakage power will be the sum of all leakage powers of all off transistors. This depends on the input and the circuit configuration of the Gate.

wish you success

You may also refer to many papers on leakage in literature. However, I can refer you to my group's papers which are following:

1. A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6702512

2. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

http://www.sciencedirect.com/science/article/pii/S002626921300253X

The most obvious way is to simulate the NAND with inputs kept static, measure the average current drawn from supply and multiply by its voltage. You may want to do it for different input combinations. Hope this helps.

you can measure the leakage currents either by measuring the power of the off transistors in the circuit or  you can obtain the total leakage current from the log file. (based on my experience with MentorGraphics Eldo simulator)

Theoretically you can measure the leakage current as following:

1. Put one NAND gate in the netlist. Apply proper supply (VDD) and ground.

2. Put input to one of the valid combinations (e.g. for 2 input NAND gate you may put 0 on both inputs)

3. Run a DC simulation and measure current through supply. It will be a negative current so you need to measure absolute value of you may multiply by -1.

4. Multiply this current to supply value. This product would give you leakage power.

5. Ideally you would like to repeat the process for many PVT corners (say FF, TT,SS/VDD=max, min/Temp=-40, 27,125)

6. Repeat this process for all other valid input combinations. Valid means either 0 or VDD. You may use .data or .alter to run all the input combinations in same file.

If the current values are extremely small (say less than 1nA) as can happen for SS_minVDD_-40Ctemp then you may instantiate many NAND gates (say 100 or 1000) and then divide the current by this factor.

Saurabh.

1) while transient simulation, measure the current through VDD,

In the graph, you will see peaks of current at the transition point (it will contribute towards dynamic power) once current stabilizes that stable current is the leakage current, measure this current for a different combination of the input and average it out

2) In the log file of the Hspice/eldo simulator you will find current that will be the leakage current of the circuit, you can cross-check it with simulation

It is better to go with the first one.