I am looking for help explaining an unknown phenomena when performing Capacitance-Voltage measurements of a MOS device utilizing insulative Bi4Ti3O12 thin films on Silicon substrates with ZnO interface layers. A detailed explanation of the fabrication an structure is included at the end of this post.
I have attached three graphs presenting my results, all measurements were performed with a bias voltage sweep of-5V to 5V, using a measuring signal of 30mV RMS with different frequencies. Measurements performed at 1MHz(pictured) show ideal MOS behaviour, with clear Accumulation, Depletion and Inversion stages. When the frequency is reduced to 100KHz the MOS behaviour remains, whilst capacitance drops increases slightly, which is explained by more dipoles being able to follow the slower measuring frequency.
When the frequency is reduced to 10Hz however, a sudden drops in capacitance can be seen at 0V. This effect is seen again when the frequency is dropped to 1 KHz. If anyone could help me explain this phenomena, I would highly appreciate it.
Best Wishes
Jamie
Sample Fabrication:
P-SI(100) substrates had SiO2 layers removed by etching with Hydrofluoric acid. Onto these etched substrates, a 20nm ZnO interface layer was deposited by Rf sputtering, followed shortly a 300nm BTO layer. Before the thin films were annealed, Ni contacts were deposited BTO and exposed silicon surfaces to ensure ohmic contact. The thin film was then annealed at 700OC in vacuum to ensure the silicon substrate did not oxidise.
The plots are indicative of dual-junction structure. Second junction depletion layer seems to be very thin ac dC/dV is large. Another option is some non-linear effect. Try to reduce the probing power and see if any changes present.
Dear David,
You said in your question that the behavior of your MIS capacitance is as expected at the frequency of 1MHz. For p-Si substrates the accumulation occurs at most negative gate voltage where the inversion occurs at most positive gate voltage voltage if it can occur at all at this high frequency. At such high frequency only accumulation and depletion are responsive while the inversion is not responsive because it is a slow process. So, yu have to tell us what is the applied bias voltage polarity of your MIS structure before going to any further discussion. If the polarity of your applied voltage is reversed then your results at 1MHz is okay. That is you have accumulation and depletion as with normal MOS capacitor.
Best wishes
I would like to thank you both for your input.
Oleg, : I will do some research into those terms that you mentioned, but you you elaborate further on what you mean?
Abdelhalim Zekry: Your observation is correct, I had the probes the incorrect way around when I performed these measurements, I will make sure to change the labeling in my final report.
This is one of the first MIS structures I have developed, and whilst the high frequency behavior (apart from the incorrect voltage labels) shows proper behaviors, I am abit concerned about the capacitance itself. References on similar materials typically have larger differences between the accumulation and inversion layers. Is it cause for concern to have such a small difference in capacitance? or is it likely an effect of the P-Si doping levels?
Best Wishes
Jamie
David,
What is the doping concentration of the p-substrate?. It seems that the doping concentration is relatively high.
The other notice is that the dielectric cost-ant of the insulator decreases largely with frequency, which may be a characteristic of titanates.
You cab build a model of your MIS capacitance and estimate its expected performance.
Best wsihes
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