If you are not limited to transistors only, you can chose the resistive load common source circuit otherwise you can use a transistor for a load (principally the same circuit). In order to properly bias the amplifier you should run SPICE DC analysis sweeping the input voltage and plot output voltage v.s input dependence. The optimal input bias point will be the one that corresponds to maximal gain (slope of the output voltage curve) . You may have to tweak the load and transistor sizes to get desired gain.  This can also be useful: http://web.mit.edu/6.012/www/SP07-L19.pdf

Hi Saumil,

I'm not an expert but I'll tell how I'll go through this exercise.

First -28 dB is actually an attenuation not gain. I assume by -28 dB you actually meant an inverting amplifier with a gain of 28 dB. So I'll continue based on the this assumption. 

First I believe you that 28 dB with a single stage on a 180 nm isn't a trivial task. I think you will end with an active load a PMOS current source. And a cascode for both the NMOS gm and the PMOS load.

1. Assuming you are using core devices lets assume the supply to be 1.3

2. Assume that your output range is 0.9 Vpp

with a 28 dB gain (25 absolute voltage gain) the input range is limited to 36 mVpp

3. This means that the input/current source bias voltages won't be affected much by the input range. rather the output range:

a. The gm driver NMOS (plus its cascode) should have a VDSAT of 200 mV or less.

b. the current source (plus its cascode) should also have a VDSAT of 200 mV or less

These two requirements are based on the output range.

4. Selecting the current bias as well will depend on the same factors as the input bias.

In addition to that you need to make sure that the current DC value is larger than the current swing during the input variation.

5. Assuming you are operating at low frequencies, couple of 100 MHz max, you would need to have a device channel length of ~ 1um to have better ro.

6. If noise is a concern you should take care of increasing the PMOS gm as it will hurt you with more noise. Also increasing the input device gm will help you in terms of noise. [Take care as most of the time this will be countering the other design requirement]

So the best procedure from my point of view is first get to a functional design.

Second check it's performance and iterate to fix each metric.

N.B. you should have some elementary lecture notes for the tradeoffs of the design as Armen was proposing. I'm adding another lecture notes for you (It's the first time I see them so don't assume these are the best, you should better look around on your own for different universities and professors.

http://ece.wpi.edu/~mcneill/4902/lectures/StudioRev_5.pdf

Final note you should get your hand dirty with multiple iterations, and mess your design up few times to really get the grasp of how the design trade-offs work. No amount of lecture notes can get you to be a real designer.

Thanks,

Mina

Thak you all for your valuable guidance. I would like to know what can be the drain current equation for short channel device  and how can i calculate velocity saturation?