Hello Sravani Vasu,

Your question is very interesting in field of digital circuit design. To answer it I've found a document which I make a citation from:

"In dual-rail encoding,8,9,22 each bit is implemented by a pair of wires, or rails. In the reset phase, both rails are low, form- ing a spacer, which indicates no valid data. During the evaluate phase, the sender asserts exactly one of the two rails high, thereby indicating the actual value of the bit (0 or 1) as well as data validity. The receiver typically uses a completion detector (CD) to identify that a valid codeword has been received. The remainder of the four-phase protocol proceeds as expected: after the dual-rail data is transmitted, ack is asserted high by the receiver, the dual-rail data is reset to zero, and ack is deasserted low by the receiver. Such an encoding is one instance of a delay-insensitive (DI) code,22 in which each codeword uniquely identifies its own validity."

Further information could be found in the article 

http://www.cs.columbia.edu/~nowick/nowick-singh-ieee-dt-11-published.pdf

thank you 91

Thank you sir. my doubt is how to apply the inputs for the first stage? first and second stage communicates with 4phase handshaking as you said. but for the first stage we have only input and its compliment available(by using inverter). how we can give spacer to the first stage?( assume its before circuit is not a dual rail asynchronous).

The inputs in the design should have a signal that strobes valid data on the bus. Otherwise you never know if data valid or not.

Take a look at Figure 4 in the document from my previous answer and the paragraph called Pipeline structure on the page 5 : "The leftmost channel has single-rail data

(datain) and a bundling signal (req0) as input"

Thank you sir for your answer