In xilinx ISE 14.7, after the synthesis is done, synthesis report shows the maximum combinational path delay. From this if I wanted to calculate Maximum frequency, it gives a different answer as in the attachments.
So, what is the correct way of calculating Maximum frequency in xilinx ise 14.7?
The post below may have some info that may be helpful:
http://myfpgablog.blogspot.com/2010/11/understand- maximum-frequency-reporting.html
https://forums.xilinx.com/t5/Synthesis/Synthesis-report-Maximum-clock-frequency/td-p/247540
Maximum frequency of operation is varied depending on the complexity of the design and the target technology. More complex design means longer combinational delay and a reduction in the maximum frequency of operation. In you table, two different multipliers in complexity thereby two different maximum frequencies.
Practically, the maximum frequency could be a bit less than the one you got from the synthesis report.
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