I have implemented current mirror Operational Transconductance Amplifier having PMOS input differential pair, two current mirrors and output cascode stage. I want to find expression for DC voltage at the output of Operational Transconductance Amplifier.
Please, shed some light on DC voltage at the output of Operational Transconductance Amplifier or tell me about any book which shows strategy to calculate the same.
Hello dear Kulbhushan Sharma ,
It's unfortunate that you have not got any answers until now.
A transconductance amplifier has (and should have) a high output impedance (Let's simplify it as output resistance since we will deal with DC), which is why the output DC voltage is not well-defined. We usually use this term, because the output resistance is large and also non-linear, as a consequence of the channel length modulation effects on the n-type and p-type transistors whose drain terminals are connected to the output node (In case of cascode structures, the output resistance will be larger).
When you leave the output terminal open circuit (infinite load resistance), this forces the currents of output nMOS and pMOS transistors to be equal.
On the other hand, because of some little offsets (or maybe large offsets due to improper design), the nominal currents of these output nMOS and pMOS transistors for DC may not be exactly equal.
The mentioned condition (output open circuit) dictates the equality of the currents of the output nMOS and pMOS transistors, which forces their currents to change from their nominal values. Even if the relative changes in the currents are very small, they typically require much larger change in the drain voltages of the nMOS and pMOS transistors due to the large output resistance (i.e. due to channel length modulation). Typically, this large change in the output voltage drives one transistor into triode region, which may be the case even when your design is a proper one (and is kind of inevitable to happen for a cascode output stage). So, the issue is not only whether we can estimate the DC output voltage value, but also whether we can keep the output transistors away from triode region.
The slight inequality of the pMOS and nMOS transistor currents is also affected by the random mismatches of the transistors and temperature gradients, etc. So, even for two identical OTAs, you may not be able to get the same DC output voltage for open circuit output (e.g. one may have a saturated output voltage close to negative supply, while the other is saturated close to the positive supply).
Consequently, I should emphasize that, it is difficult to estimate the DC output voltage of such a circuit (for open circuit output).
During simulation, for open circuit output, you can set the output DC voltage equal to zero Volt by applying a proper offset voltage source at the input (or an offset current source at the output).
Finally I need to mention that, in an application, the utilized local or global feedback usually helps the output DC voltage to be stabilized (I added this last paragrapgh, because, I don't want my comments above to be perceived as "the DC output voltage of an OTA is something very difficult to take under control").
Best regards...
I want to add 2 more practical methods to stabilize the DC output voltage VO (at zero Volt - for instance) during simulation.
1. You can apply a DC offset current source (IO-os) to the output node. For a certain value IO-os (which you need to find) the output DC output voltage will come to zero Volt (or close to zero Volt, which guarantees the desired proper operation of the output MOSFETs). IO-os value can be found with 2 methods (I assume the design is a proper one, so there is no substantial systematic offset problems):
- Connect the IO-os current source to the output node and run a DC sweep for IO-os and check the value of it for which VO is crossing zero (P.S.: It may cross steeply, so you may need to run a second sweep with a narrower current sweep range and shorter current steps to determine the value more precisely).
- or, just connect the output node to ground (No need for an IO-os current source). The value and sign of the current flowing from the output node to ground will directly provide the required IO-os value (Because, you are forcing the output voltage to ground level, which mandates the inequality current (i.e. IO-os) to flow towards (or from) the ground)
2. Connecting a very large inductor between the output node and ground will help the offset current to be released from the output node for DC but will not affect AC (down to very low frequencies) as long as it value is sufficiently large. This value can be as large as you need, since there is no limit for the values to be used in the simulation. However, if the value is not large enough, you may have problems in low frequency AC behavior due to effects of the inductor. The inductor behaves like a short circuit for DC steady state and approx. like an open circuit for AC (The second one requires a sufficiently large L value).
- You can keep the inductor in the complete system. It will stabilize the DC output voltage of the OTA even for open-loop cases. For AC, the inductor will simply be open-circuit (for a large L).
Best regards...
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