I fabricate GFETs on SiO2. the Devices have to be washed with acetone DMF and water for cleaning after lithography and all the fabrication process is over. Finally, to dry the device and remove any residual water, the devices are then annealed in vacuum at around 250C ~300C. The leakage current is always very high due to unknown reasons. Our SiO2 thickness is 285 nm on Si of 0.45 nm. It shouldn’t be easy for such a thick dielectric to breakdown. Please suggest me any possible explanation of leakage current or solution to avoid this large leakage. I believe that I am making some mistake again and again as leakage is high for all the devices I fabricated. Thanks
Dear Saleem
There is not much information about the device. Also how much is the leakage also not mentioned. How big size are your source and drain pads ? Is one of electrode (source or drain ) is in common with several devices ? I mean one possibility for such leakage is due to the large area of source, drain electrodes. If the leakage happens with this then you should decrease the electrodes size. Also isolate every devices.
Secondly, sometimes this may happen with parameter chosen for measurement. From my experience, I recommend to provide little large value of compliance i.e. compliance current. If you give too small value for compliance, it may show leakage. But in actual there will not be leakage. So check again with little high compliance (let us say 10E-8 A, for your 285 nm SiO2). If leakage was due to this thing, it will be solved.
Good luck
Device is GFET, Leakage is 0.1 mA and even higher sometime. Source and drain pads are 500 um is size. each device in the array has its own source and drain pads and devices have been isolated by etching the Graphene. The compliance value I use is 0.005 A. For the larger values of compliance, the back-gate voltage limits it to lower values automatically and so the measurements in my given range of voltages are not possible.
what exactly is the significance of "compliance"? Does it allow us to limit the leakage current? If so, we cannot claim that our devices intrinsically give lower leakage current. We limit it ourselves instead.
0.005 A is too high for current compliance. Generally give the compliance 1E-9 A. Since the leakage on your device is 0.1 A, there should be some more thing wrong on the device or the measurement process. What is the channel current ? Also start to measure with low value of the drain voltage.
It will be better to make the one new device and check again. Let use these parameters for measurement : Drain voltage 1 mV, Gate compliance 1 nA, Gate sweep range -25 to + 25 V. Later on you can increase the gate sweep range. I hope you will avoid the leakage problem this time.
Dear Saleem,
Have you solved your problem?..i have faced the same problem for the last couple of months....i am fabricating metal oxide TFT using 100 and 300 nm SiO2 dielectric layer and the leakage current is always very large near to 0.5mA. Could you please share me your experience if you already solve it...Thank you very much.
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