The industry uses low-k dielectrics in the interconnection network.

To elaborate upon Stephen's remarks:  modern CMOS devices use 8-12 metal layers on top of the active devices.  Thus, a large proportion of the total capacitance seen globally is due to the metal layers.  (The lower metal layers in e.g. a 28-nm process are extremely thin, so they also contribute substantial resistive losses.)  The gates or fins and lowest metal layers are insulated by silicon dioxide, k=4, because of its mechanical stability and process robustness.  Upper metal layers use dielectrics with lower relative dielectric constant  (around 2.5-3.3), although very-low-K materials like foams and polymers have turned out to lack the ability to survive the CMOS process.  In older processes, fluorinated silicon dioxide was used; in more modern processes, methylated silicon dioxide is often employed.  

Designers can optimize their designs for reduced capacitance, but typically as a tradeoff with e.g. connectivity.  CAD tools provide extraction of expected metal-to-metal capacitances for a given layout, permitting the designer to reduce coupling on critical lines through routing other stuff away.  However, this becomes extremely difficult in dense layouts with mixed-signal functionality, and in modern processes design rules (limits on line width, spacing, density, and so on) also constrain layout variation. 

The geometry of the CMOS transistors themselves is optimized by the use of spacer layers and implants to minimize the amount of charge that doesn't modulate the channel.  FinFETs, used at 20 nm and below, have intrinsically better performance in this context, since they wrap around the active silicon.  Nanowires or wraparound FETs do even better, but at considerable cost in process complexity. 

Hope that helps.

Parasitic capacitances are integral part of the elctronic devices including MOS transistors. They are either due to MIM, MOS capacitances or junction capacitances.

These capacitances ca be decrease by decreasing their areas or the increasing the thickness of the insulating layers. The most effective method is to minimize the area of the capacitors by scaling down the devices. Scaled devices have smaller cpacitance values because of their size shrinking.

This from the point of view of the device structure. As for the device operation one can use the socalled current mode circuits in which the device is operated as a current source far from the on and off switching of the parasitic capacitance. The basic building block of the current mode circuit is the differential amplifier or the current mode logic.

This is a short hint giving only the ideas but you can consult the specialized literature.

Thanks,

Stephen, Daniel and Abdelhalim sir,

first of all I want to express my warm welcome to all of you . your guidance and answer to the query is very helpful for me to clear my point. Abdelhalim sir I have one futher question to you Is current mode devices do not suffer from parasitic effects? Looking forward for a reply from your side.

thanks

Dear Pawan,

as I see it, all has been said (Stephan, Daniel, Abdelhalim) apart perhaps of what you really mean by stray capacitance. If stray means unwanted and unneccessary, then removal would be the way forward. If  stray means unwanted time delays, then there might be/are also other methods to try to avoid them, not yet mentioned here. Problem is that , as already pointed out, any device is 3-dimensional and will always have some capacitance and unwanted time effects connected with it. In one of our studies of p-n power diodes , we tried to cure these effects by introducing deep recombination defects into structure, so that reversing the polarity became faster. Strange that sometimes making things less perfect makes them work better. The point I am trying to make is that one has to analyse carefully every capacitive effect in order to find an optimal solution. But my general impression is that the industry has tuned all these effects to perfection !?

With best regards

Petr

Very true petr

thanks

Dear Pawan

Dear Petr,

When you introduce recombination centers in the material by deep lying energy levels in the energy gap, like gold in silicon or irradiating the material with energetic electrons, you decrease the minority carrier life time and thereby you enhance the recombination process in the reverse recovery process of the diode. 

In fact, one can see this as you decrease the so called diffusion capacitance of the diode. It is also a parasitic capacitance. The excess charge storage occurs in bipolar devices when forward biased.

I spoke about an other operating methods of the circuits, the current mode of operation

which limits the operating voltage swing such that the device operates always in the active mode of operation far from the off and the on state where parasitic capacitors need to be charged and discharged with the full voltage swing in case of the voltage operation.

As an example assume that you have a differential amplifier with two symmetrical transistors. When the input voltage difference is zero, then the the total emitter current will be divided equally and the collector currents will be equal. You need only a difference voltage of about 50 mV to steer the total current to one of the transistor, that is to switch the current from one transistor to the other. THerefore the current switching needs only a small voltage swing and therefore much smaller charging and discharging time compared with full voltage swing voltage mode operation. You find in the literature many good literature speaking about the merits of the current mode operation.

Best wishes

Dear Abdehalim (and Pawan),

thank you for the e-mail. My main point has been just to point out what kind considerations in regards the "parasitic" capacitances one has to make when designing one's device. 

As far as the introducing deep recombination centres into p-n junction of the power diode , there we were (well our customer)  really interested in the voltage mode of operation .  

I would not really agree that the argument goes ...introducing the recombination centres decreases the minority carrier life time... It is in fact the other way round , namely that increased density of the deep levels (in our case there were two levels after He bombardment and annealing) increases the recombination and thereby the apparent minority carrier life time.  My interest in this project were the fundamental aspects of mobile electrical charge transport rather than the actual device performance/optimisation. 

However, your comment regarding the current operation of the devices sounds quite interesting, although my feeling has always been that the constant/variable current sources were not as fast as the voltage sources. Also, our devices had to be switched from full off state to full on state (yes large current, no current) and therefore I do not see how current operation could help. But I migh have misunderstood something. 

With best regards

Petr