Hi Mohammad Faisal Akhtar ,

I think this spike is mainly caused by the capacitance between drain and gate of Q2: When Q1 is switched on, VDS of Q2 increases, and part of this edge is coupled to the gate.

Of course, the spike becomes critical only if Q2 is (partly) switched on by it. There are at least two ways to reduce the spike:

1. By adding a capacitor between gate and source of Q2. This is not advisable because it would increase the switching times of Q2.

2. By driving the gate of Q2 with a lower impedance. Your drawing doesn't show the drivers, so I don't know your circuit. If you don't use them already, there are integrated MOSFET drivers with the capability to source/sink up to 3 .. 5 A.

Hope this helps.

You may have a look at this application note: https://www.onsemi.com/pub/collateral/an-5073.pdf, it describes the issue in detail. As Joerg Fricke wrote, the reason for the spike is the Miller capacitance of the low-side MOSFET, i.e. its reverse transfer capacitance Crss.

To minimize the spikes, the easiest way is to use a MOSFET with a low Miller capacitance. Modern MOSFETs have a Miller capacitance of a few pF only, this should solve the problem.

The other way is to use a stronger driver - preferably with the Miller clamping described in the abovementioned application note. You can also try to implement the Fig. 5 from the application note, but this is usually the last step if all other simpler solutions failed.

If the MOSFET drivers are not a part of the used step-down (buck) controller, you may also consider to use bipolar gate voltages for driving the MOSFET. With a negative bias instead of a 0-V voltage, the observed spike will not reach the threshold voltage of the MOSFET and will not cause any cross-conduction more. This technique is often used for driving IGBTs, but can also be used for MOSFETs. There are dedicated driver circuits available on the market that support the bipolar gate voltages.