In Cadence Virtuoso, we can draw a schematic of the circuit with active and passive components, and then we can launch ADEXL for the layout. Then, according to the value of the capacitor, it's layout comes. But, how do we find the value from the layout window, only after DRC?
Hi, if you have instantiated in the schematic a capacitor from your target technology library, using LayoutXL you can launch Connectivity>Generate>All from source... and the capacitor layout must appear as a cell with properties you can check pressing Q.
But if you have drawn the capacitor 'by hand' the only way to check its value is to perform a circuit extraction and find it on the netlist, or run a parasitic extraction, find the equivalent cell placed by the extractor and quesry its properties.
Try to see the layout properties, may the value is there.
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