Shobhit Singh

8 Questions 9 Answers 0 Followers

Questions related from Shobhit Singh

What is the latest IC released for a universal filter?

Please tell me any website or detail how to search for any new IC released in the market for any particular field. For eg. gsmarena.com for any new mobile launched with its detailed features and...

08 July 2014 4,177 2 View

What we can conclude from sensitivity result obtained by ADEL in Virtuoso?

I have done sensitivity analysis using ADEL in Cadence virtuoso for my design for ac and dc base. I have attached some part of the result of sensitivity analysis for ac base .What does this result...

30 April 2014 7,680 1 View

How to connect MIM capacitor in Virtuoso Layout XL (Cadence)?

I have used a grounded MIM capacitor at output load, so please tell how to do connection for it in Virtuoso Layout XL. For eg. when I connected a simple capacitor with vdd and ground and drawn the...

07 January 2014 1,000 11 View

How to merge multiple graphs in a single window in Cadence virtuoso?

eg. I am plotting waveforms like ac response for different values of load capacitance, how to get all the plots in a single waveform to show the variations?

29 December 2013 4,015 4 View

Cadence layout error, please tell how to remove?

1. nwell_term_stamperrorMult 2. PSUB_StampError_Mult

29 December 2013 2,470 3 View

How to do corner analysis in cadence post layout simulation?

After doing RC Extraction of layout (after DRC and LVS) what is the next step? What is corner analysis.

29 December 2013 2,698 4 View

How can I find out the capacitor value from the layout in Cadence Virtuoso, if we have not generated it from schematic?

In Cadence Virtuoso, we can draw a schematic of the circuit with active and passive components, and then we can launch ADEXL for the layout. Then, according to the value of the capacitor, it's...

26 December 2013 3,271 2 View

How can I find the area of layout in Cadence Virtuoso, and how can I make a capacitor in the layout?

When I am using a capacitance value of less than 1 pf from gpdk 180nm library, i.e MIM capacitor or nmoscap, it can be directly generated in layout XL. But how do I export when the value of cap is...

26 December 2013 5,704 2 View