Hi Maryam, before being able to answer I have two questions:

Your circuit looks a bit unfamiliar: Usually, a 16-bit-adder has 16 A-inputs and 16 B-inputs (i. e. a 16-bit integer A and a 16-bit integer B are presented to the adder), and only the carry signal is cascaded. Is this the case with your circuit, too, or do you really feed the sum output and the C output of one stage into the inputs of the next stage, for test purposes?

Since your simulation is at transistor level, could you please provide the circuit of one cell at this level?

Thanks Joerg Fricke!

The first case you mentioned is about a RCA and the second case is a 16-bit test-bed of full adder for test driving capability of 1-bit full-adder cell designed.

To answer your second question I can say my 1-bit design is based on a hybrid structure and in comparison with two other designs acts better, but when it lies in 16-bit test-bed, it shows unstable rise/fall in one of input transition, whereas other designs  have proper output signals.

Hello Maryam, without knowing the details of your circuit the following points come to mind:

Provided that all 16 time axes are synchronous, as usual, your circuit shows an uncanny speed: The rise time of output 1 looks like virtually zero at this time scale, and there is virtually no delay time from output 1 to the first reaction of output 16. If this is not an artefact introduced by the simulation: My congratulation! I'm waiting anxiously for your circuits to become commercially available. :-)

The plateau midway between the low state and the high state reminds me on metastability seen in flipflops. But in order to get metastability the circuit must have some kind of feedback loop. I guess the only feedback in your adders are the reverse capacitances (between drain and gate), provided you are using some kind of FETs. In reality, another feedback loop is always provided by the supply rails but I assume your simulation uses either ideal supply voltages or you have attached enough and suitable capacitors between the rails.

My final (blind) guess: You might have fine-tuned the parameters of your circuit first in order to get the fastest reaction possible. Since the speed increases with decreasing signal voltage swing, this resulted in a circuit whose high level output voltage is just above the threshold input voltage. Consequently, your (effective) rise time is not defined by 10% and 90% (or so) of the complete output voltage swing but, say, from 10% to 97%. While some output voltages of your adder cascade are still below this 97%, the charge on the gates increases but the FETs are in an intermediate state where the feedback via the reverse capacitances causes weak oscillations.

If this were true, redoing a little bit of the tuning could result in slightly slower adders and shortened intermediate states. Another idea: If the input thresholds were really asymmetric (e.g. 10% / 97%) you could add (just for the sake of experiment) ideal voltage sources between each output and the following input in order to shift the input voltage a little bit upwards.

Thanks for taking your time to respond and congratulation to your depth!

I am simulating adders with CNTFETs and to make pwl input voltage sources, I defined their timing manually from input signals available in most articles! In fact I did not find a automatic way to generate pulse codes in hspice.

Attached picture shows the rise time of out1 and out16 and the delay time of stable and unstable rises. the threshould level is 50% of vdd to determine delay time.

I searched about glitches, metastability and runt pulse and found that there are the oscilloscopes witch can do triggering in noisy pulses too. Moreover there are techniques that can calibrate the transient signals. but I dont know how!? Should I change delay triggers definition on unstable edges?

Something that caught my attention is that why unstable state occure only on edges (rise/falls) but not on levels?!

About intrinsic capacitors I found their equation in library for example:

Cgd=abs(charge_vds(V(Vdrain),V(Vsource),V(phib,Gnd))/Vg_to_phib(V(Vdrain),V(Vsource),V(phib,Gnd))*Lg) for CNTFETs.

About Cload I used the same capacitance for 1-bit adder and 16-bit adder test-bed!

Also the high voltage is about 2 to 3 times of Vth.

In addition, I returned the parameter values to default to increase delay but glitches became greater!

Hi Maryam, I'll have to meditate a little bit about the information to be gained from the new attached picture. For the time being, I restrict my answer to your observation that oscillations occur only on edges:

In order to oscillate at all, the total gain of all elements which form the feedback loop has to be >= 1. The Uout-over-Uin-curve of all voltage controlled logic circuits is virtually horizontal at both ends, and has an ascent or a descent with a gradient > 1 resp. < -1 in the middle part. So, if Uout = Uoutmin or Uout = Uoutmax the gain of the circuit is virtually zero, and thus a condition necassary for oscillation is not met.

Another question: Could you please provide a picture of the input signals A, B, and Cin fitting as exactly as possible to your last picture of the output signals?

 Thanks for your attention!

Sum output attached too and also total test pattern(out2 to out15 have been removed). In fact glitches occure when 2 of inputs want to change at the same time. If I have to change 1-bit FA structure, delays or other parameters may lose their improvements.

Hi Maryam, after looking at your last three pictures I'm certain that the phenomenon is not oscillation but the accumulation of glitches.

I see no way to completely avoid glitches of the sum output because the related Karnaugh map shows a checkerboard pattern, and consequently no redundancy can be added. In most applications, the input and output signals are clocked into registers; thus the penalty for short glitches is just a small delay of the clock of the output register. Since glitches in the sum output occur only if more than one input changes (this is true for your sum0), cascading in ripple carry adders, for example, poses no problem because after the initial phase only the Cin inputs change.

However Cout looks like a good candidate for improvement: With two input signals changing, Cout0 should show no glitches at all but it does even with one changing input, e. g. at 30 ns. Is Cout derived directly from the input signals by a two-level tree of gates? If not, it should be. If you've got a schematics sketch of your adder on the logic level, I would like to have a look at it.

Did you try a test bed with sum outputs connected to *two* inputs, and Cout outputs connected to only one input of the successor? With improved Cout, that should look much nicer than the current results.

Welcome Maryam, welcome Joerg,

Good discussion. Yes , what is seen in the last pictures are glitches because the difference in propagation delay times of the signals. The circuit is a cascaded combinational one composed of logic gates, which can differentiate the  two input signals leading to the formation of glitches.The phenomenon of glitches is a well known one and occurs in unsynchronised or (rippled) cascaded logic circuits having different propagation paths.

In the first picture the problem is that there is slow rise of the the edge with time as the rank of the output increases. This may be unacceptable as in logic. It is not the ringing in the output which is serious. As a remedy for this you have to put drivers in the proper points in the signal path to regenerate it. The glitches themselves will not affect the logic value evaluation at the output. More serious that the slow rise may last longer than allowed to evaluate correctly the signal level.

wish you success

Joerg Fricke and  Abdelhalim Zekry thank you very much and sorry for my delay in response.

Joerg Fricke, I simulated FA cell in 7 cascaded cells with sum to 2 input, because in this case odd number of cells can be cascaded to have a sum at first output and a cout at second output according to attached picture and finally glitches disappered!!! :) but I still have a quastion, Can I use the test-bed for even cells which is shown in the picture?

Abdelhalim Zekry, I used two cascaded inverter at first of inverter but I should say that I measured delay from before input inverters to before output inverters (because of simplicity of delay computations).

Maryam,

welcome,

Yes introducing the drivers will add propagation delay but the edges of the signals will be more sharp and the logic transition will be faster.

concerning the block diagram of the staged adder, it confused me, since in every stage you input two bits in addition to the carry from the previous stage. That is you add Ai +Bi+ Ci-1.Where i is the stage order. The logic parameter which needs regeneration is the carry. Ci-1 because Ai and Bi are fresh inputs.

wish you success

Maryam, this is not jitter. This is simply transition time propagation effect barring ripples in waveforms. 

Use strong drivers (with high width transistors) in the output stage of your adders and see it disappear.

Good luck.

Read more on transition time propagation effect at paripath.com/book.

www.paripath.com/book

Thanks all of you very much!

Abdelhalim Zekry, as far as I know only at first stage of test-bed, adding is done and after that sum and carry are propagated.

Rohit Sharma, the output signals after two inverters of test-bed were without glitches, but I don't want to add two other cascaded inverters in FA cell. Also increasing width of output inverters didn't remove unstable states. Simulation results showed which already my only remedy is changing the test-bed ( to 2 input Sum).

Thanks, Majid Amini Valashani

Whereas the test bed I used has been used in many articles, but I agree with the reasons of the reffered article about drawbacks of that. On the other hand, I think the test bed which has been introduced after that to use, is for 1 bit adders, so can be this test bed a proper case to test driving capability of adders for example 16 bits?